Field-Programmable Gate Arrays

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Verilog Draggable Window Library

HWGUI is a Verilog library which generates windows with captions on a VGA display. This uses no microprocessors; a stat...
1 comments posted 20yrs
posted by tbfleming
1 comments posted 20yrs posted by tbfleming

Looking for DDC/DUC customizable cores

Hi all, Just as the subject says I am looking at what is available besides Xilinx own cores. Basic requirements: Comple...
0 comments posted 20yrs
posted by mbmsv
0 comments posted 20yrs posted by mbmsv

Cyclone II PCI & Pin Swapping

I'm implementing a PCI104+ board which will have the opencores PCI bridge core. I've started with the suggested layout...
1 comments posted 20yrs
posted by joey
1 comments posted 20yrs posted by joey

DCM

Does any buddy know How DCM work and does it require an input clock sigal or a output signal from external oscillator ca...
2 comments posted 20yrs
posted by fpgalearner
2 comments posted 20yrs posted by fpgalearner

Hold Time Violations in Virtex4

Hello, Iam getting the following hold time violation in my design. Its happen on the address inputs to a instantiated r...
1 comments posted 20yrs
posted by brijesh_xyz
1 comments posted 20yrs posted by brijesh_xyz

CoolRunner Pins during Programming

I noticed that the CoolRunner (XPLA3) sets all of the pins (at least the ones I can monitor) high during in system prog...
1 comments posted 20yrs
posted by emh203
1 comments posted 20yrs posted by emh203

ANNC: ISE/WebPACK 8.1i tutorial available

We have released a new version of our ISE/WebPACK tutorial that is updated to version 8.1i: http://www.xess.com/appnotes...
0 comments posted 20yrs
posted by devb
0 comments posted 20yrs posted by devb

SystemACE bootloader for PowerPC on Virtex4 FX

Hi, I am looking for a small bootloader (small because I'd like it to be in BRAM) that can load a PowerPC ELF file (pos...
11 comments posted 20yrs
posted by jon
11 comments posted 20yrs posted by jon

disappointing 550Mhz performance of V5 DSP slices

Hello, Can anyone give i explanation for the disappointing 550Mhz performance of V5 DSP slices? Couldn't we hope 1GHz m...
39 comments posted 20yrs
posted by airtom
39 comments posted 20yrs posted by airtom

EdaXML

Dear all, Mid-Google about something largely unrelated I spotted references to "EdaXML" which seems to be an XML-ified...
0 comments posted 20yrs
posted by petermendham
0 comments posted 20yrs posted by petermendham

ADC implementation on FPGA ?

Hi ! I would know if , to your mind, it may be possible to implement a 16 bit Analog-to-Digital Converter on a FPGA ( li...
8 comments posted 20yrs
posted by romaingoron
8 comments posted 20yrs posted by romaingoron

SPI master

Are there any examples out there that i can take as reference and build my SPI master on Virtex 4 FX Thanks
2 comments posted 20yrs
posted by fpgalearner
2 comments posted 20yrs posted by fpgalearner

XilKernel and Budgeting

Does any buddy have any idea or guide me to some document explaing how the budgeting can be done in XilKernel on PP405....
0 comments posted 20yrs
posted by fpgalearner
0 comments posted 20yrs posted by fpgalearner

Shared Memory

Hi, A basic question what are the possible ways to make PowerPC communciate with the FPGA fabric. I know the Coreconnec...
0 comments posted 20yrs
posted by fpgalearner
0 comments posted 20yrs posted by fpgalearner