ADC implementation on FPGA ?

Scope schrieb:

Search the Xilinx Website for application notes. Or search the USPTO patent database for "Austin Lesea".

Kolja Sulimma

What's the speed ..? Voltage levels ..? Cost ..? Complexity ..?

up to 100 Mhz.

analog input signal is between -1V and 1V

cost is not a problem

What do you want to say with the term "complexity" ?

I need to convert it to an 8 bits format.

Thanks for your replies

Linearity ? SFDR ?

The first figure was 16 bits ? Perhaps this is homework ?

The killer in the ADC is that letter A = Analog. You can do digital stuff in FPGA, but not analog. You can use the FPGA to minimise the Analog, but it cannot be removed entirely. SigmaDelta ADCs are one path, but not for 100MHz sample rates... Sawtooth + Comparitor gives a low performance ADC, a long way from 16 bits. 8 bits then needs a time resolve of 39ps - you get the idea....

-jg

I think it is all feasable. The problem is that a solution that works for you doesn't match the needs for 99% of the other potential users. So it is hard to obtain such a specific function to a programmable device. Maybe one day someone will be able to build a configurable or programmable ADC. (Austin, is this allready patented? Otherwise I might be a candidate) Then it will be useful on an FPGA. And this is true for other analog functions (not to mention the process difference between analog and digital).

Regards

Luc

Luc,

-snip-

Yes, it is. I did (for Xilinx).

Since then, I also believe our IC Design Centre (note spelling) in Dublin, Ireland has also filed quite a few more on that subject.

You are correct, however. It is very hard to make everyone happy, so we have to see just how many smiles we get for a proposed feature, and weigh that against the costs (area, yield, market gained/lost, competition, etc).

It really doesn't matter what it is: PCI? PCIe? EMAC? PPC? PLL? DLL? ECC? FIFO? MGT? they are require some study, and we may not get them right the first time we do them (since anything new is a real risk).

Quite a balancing act.

Austin

About the fastest ADC you can make from digital logic is an R-2R network ladder successive approximation ADC. You first generate an analog voltage with the the R-2R network driven my MOS outputs. 16 bits are beyond .. I'd guess about 10 bits to be feasible. The DAC voltage would of cource be within the output voltage range. Then you have an external comparator telling whether the value is too low or too high. 100MSamples are too fast too. You cannot work with high impedance stuff there anymore. The R-2R network with 100 Ohms each ? That is a lot of current.

Rene

Rene Tschaggelar schrieb:

With all necessary respect to tweaks, tricks and clever design, but there ARE reasons why certain functions like 100 MSps ADCs are discrete components. I dont think that ther are pure rip-off. So if you want a 100 Msps ADC, buy one and connect it to the FPGA. Done.

Regards Falk

P.S. If all you got is a hammer, everything looks like a nail.