Hi there guys, I'm after some help with creating a VHDL testbench model for Root Complex Emulation.
My system has an FPGA with one PCIe Endpoint that is connected to a uP that has in-built Root Complex.
To test the FPGA i obviously need to drive the differential inputs at the PCIe interface (via 8b/10b). Although this sounds like a mammoth task, my PCIe interface will support only a small subset of features e.g.
- only 1 lane - only one Traffic Class - only one virtual channel (hence no arbitration) - no MSI support - no INTx - no Advanced error reporting - always await ack before proceeding with new request
I "don't think" i'll have problems generating/sequencing the TLP's but i am having trouble understanding/getting info about what happens directly after power-up (...called enumeration !?) with regards the set-up sequencing - e.g. negotiation of lane widths and frequency of operation, training the link etc - basically everything that needs to be done before the link becomes useable.
A N Y help/tips/pointers either with this Q or just in general regarding PCIe would be greatly appreciated.