Field-Programmable Gate Arrays

Xilinx ML461 memory board, whats the real story?

We purchased an ML461 board in Aug of 05 for $6000 from Avnet. If I follow the documention that came with the board, it...

3 comments posted 20yrs

posted by lecroy7200

3 comments posted 20yrs posted by lecroy7200

Raggedstone1 Brackets

For those of asking for Raggedstone1 brackets we have them in now. Item will appear on our shop site in due course. Joh...

0 comments posted 20yrs

posted by removethisthenleavejea

0 comments posted 20yrs posted by removethisthenleavejea

PicoBlaze and DDR Ram

Hello. I just started looking at Picoblaze. Has anyone completed a Picoblaze and DDR RAM implementation? Or does anyone...

4 comments posted 20yrs

posted by karrelsj

4 comments posted 20yrs posted by karrelsj

Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?

Hi Guys, I need a C Simulation of some Floating Point Cores from the Xilinx coregen. I thought about automatically conv...

8 comments posted 20yrs

posted by sheinzle

8 comments posted 20yrs posted by sheinzle

Synthesis problem with ranged integer

Hi all, I encountered problems synthesizing following VHDL-code with Altera Quartus 5.1. Although simulation with Model...

0 comments posted 20yrs

posted by Hendrik.Eeckhaut

0 comments posted 20yrs posted by Hendrik.Eeckhaut

VHDL model for Micron SDRAM simulation ?

Hello all, I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 memory but I can not find anymore...

6 comments posted 20yrs

posted by t

6 comments posted 20yrs posted by t

problem in simulating FFT core on ISE 7.1

hi im using xilinx ISE 7.1i with modelsim XE 6.0 starter in verilog....i have been trying to simulate FFT core on model...

1 comments posted 20yrs

posted by tamaniajavaid

1 comments posted 20yrs posted by tamaniajavaid

Test:PRBS

I'm looking for the simplest and highest performance possible way to create a PRBS-7 sequence in a Virtex4 FPGA. Any goo...

1 comments posted 20yrs

posted by avl

1 comments posted 20yrs posted by avl

multisource on signal in XPS

hey all, We are working on platform studio trying to make multicore processors. Theres one error "Multisource on signal...

9 comments posted 20yrs

posted by vidyutg

9 comments posted 20yrs posted by vidyutg

newbie wants to do VHDL on an FPGA

Hello folks, I have done FPGA design some years ago using a Schematic Design tool from Xilinx, so I am not totally "gre...

12 comments posted 20yrs

posted by frankgerlach

12 comments posted 20yrs posted by frankgerlach

Spartan3E Starter kit on Linux?

When I first unpacked my S3Esk and tried it out, I used Chipscope on a WinXP system to download bitstreams. Chipscope i...

0 comments posted 20yrs

posted by ebrombaugh.invalid.

0 comments posted 20yrs posted by ebrombaugh.invalid.

no ram core simulation with free Ise ?

wich kind of simulator should i download or purchase for include in simulation the ram genarated with core generator?tha...

11 comments posted 20yrs

posted by blisca

11 comments posted 20yrs posted by blisca

Xilinx cable drivers for Linux 2.6.16?

Has anybody managed to compile the Xilinx cable drivers for Linux kernel 2.6 available here:...

1 comments posted 20yrs

posted by wzab

1 comments posted 20yrs posted by wzab

Spartan3 or 3E pins to GND

Hi, Is it possible to programmatically configure pins of an Spartan3 or 3E as ground signals? I mean, not only configur...

4 comments posted 20yrs

posted by jaime.aranguren

4 comments posted 20yrs posted by jaime.aranguren

Achieving timing in Xilinx EDK designs

Hi all, I was wondering if anyone would be willing to share their experiences with regards to what can be done when a d...

8 comments posted 20yrs

posted by mbmsv

8 comments posted 20yrs posted by mbmsv