Latest threads in Field-Programmable Gate Arrays

ISE WebPack 8.2

Does anyone know if the 8.2 version of the ISE WebPack will support a wider range of devices or not? I'm particularly in...

5 20yrs

enquiries

5 20yrs enquiries

Xilinx ML461 memory board, whats the real story?

We purchased an ML461 board in Aug of 05 for $6000 from Avnet. If I follow the documention that came with the board, it...

3 20yrs

lecroy7200

3 20yrs lecroy7200

Raggedstone1 Brackets

For those of asking for Raggedstone1 brackets we have them in now. Item will appear on our shop site in due course. Joh...

0 20yrs

removethisthenleavejea

0 20yrs removethisthenleavejea

PicoBlaze and DDR Ram

Hello. I just started looking at Picoblaze. Has anyone completed a Picoblaze and DDR RAM implementation? Or does anyone...

4 20yrs

karrelsj

4 20yrs karrelsj

Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?

Hi Guys, I need a C Simulation of some Floating Point Cores from the Xilinx coregen. I thought about automatically conv...

8 20yrs

sheinzle

8 20yrs sheinzle

Synthesis problem with ranged integer

Hi all, I encountered problems synthesizing following VHDL-code with Altera Quartus 5.1. Although simulation with Model...

0 20yrs

Hendrik.Eeckhaut

0 20yrs Hendrik.Eeckhaut

VHDL model for Micron SDRAM simulation ?

Hello all, I'm desigining a Xilinx FPGA with a sdram controller for a MT48LC8M16A2-75 memory but I can not find anymore...

6 20yrs

t

6 20yrs t

problem in simulating FFT core on ISE 7.1

hi im using xilinx ISE 7.1i with modelsim XE 6.0 starter in verilog....i have been trying to simulate FFT core on model...

1 20yrs

tamaniajavaid

1 20yrs tamaniajavaid

Test:PRBS

I'm looking for the simplest and highest performance possible way to create a PRBS-7 sequence in a Virtex4 FPGA. Any goo...

1 20yrs

avl

1 20yrs avl

multisource on signal in XPS

hey all, We are working on platform studio trying to make multicore processors. Theres one error "Multisource on signal...

9 20yrs

vidyutg

9 20yrs vidyutg

newbie wants to do VHDL on an FPGA

Hello folks, I have done FPGA design some years ago using a Schematic Design tool from Xilinx, so I am not totally "gre...

12 20yrs

frankgerlach

12 20yrs frankgerlach

Spartan3E Starter kit on Linux?

When I first unpacked my S3Esk and tried it out, I used Chipscope on a WinXP system to download bitstreams. Chipscope i...

0 20yrs

ebrombaugh.invalid.

0 20yrs ebrombaugh.invalid.

no ram core simulation with free Ise ?

wich kind of simulator should i download or purchase for include in simulation the ram genarated with core generator?tha...

11 20yrs

blisca

11 20yrs blisca

Xilinx cable drivers for Linux 2.6.16?

Has anybody managed to compile the Xilinx cable drivers for Linux kernel 2.6 available here:...

1 20yrs

wzab

1 20yrs wzab

Spartan3 or 3E pins to GND

Hi, Is it possible to programmatically configure pins of an Spartan3 or 3E as ground signals? I mean, not only configur...

4 20yrs

jaime.aranguren

4 20yrs jaime.aranguren

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