PicoBlaze and DDR Ram


I just started looking at Picoblaze. Has anyone completed a Picoblaze and DDR RAM implementation? Or does anyone have any strong opinions on this issue. My main goal is to store program data on RAM and access it with Picoblaze. I see OpenCores has a DDR/SDRAM controller...

Thanks for your constructive ideas.

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Reply to
Peter Alfke

karrelsj schrieb:

I guess this is the wrong combination. Picoblaze is just a small 8 bit Micro, with only 256/1024 (Spartan-2/Spartan-3) words of instruction space directly addressable. If you need mor program space,

a) use two or more picoblaze, the are small b) use bank switching to access multiple banks of BRAM

Regards Falk

Reply to
Falk Brunner

Do you mean a large data-space in DDR, and that the PicoBlaze runs from Block Ram in the FPGA ? That would be do-able, and you could add features like the Serial FLASH devices have, which is auto-inc of Rd/Wr address, for continual access. ( that saves a lot of address thrashing )

If you needed more code, two bock RAMS, with reload-flip support in the FPGA, would allow the DDR behave like a HardDisk (from the code perspective).

What split and sizes do you need for Code/data ?


Reply to
Jim Granville

Thanks for everyones comments. Anyone have any suggestions on getting started monkeying around with RAM controllers? I didn't have picoblaze in mind for a specific task, rather just playing around getting my feet wet. I would like to work with a basic setup to start out. Load program data from RAM, and then advance into modifying a controller to decrypt data as it brings it it.

Anyone have any good starting points to "ease" me into this world. Implementing a RAM controller tutorial...


Jim Granville wrote:

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