Field-Programmable Gate Arrays

detecting gnd

I want to make a FPGA/CPLD test board to plug into a socket to test the connectivity of the socket. Does anyone know of...

1 comments posted 20yrs

posted by colin_toogood

1 comments posted 20yrs posted by colin_toogood

Re: Can a BUFGMUX drive a global clock in the Spartan-3?

Hi James, Can you tell me specifically what document you are looking at (document number, version, date)? I looked at S...

0 comments posted 20yrs

posted by eric.crabill

0 comments posted 20yrs posted by eric.crabill

Fastest platform to run ISE?

Hi all, I was wondering which PC upgrades can make ISE to run faster? For example, can it take advantage of dual CPU, a...

9 comments posted 20yrs

posted by mbmsv

9 comments posted 20yrs posted by mbmsv

debouncing a switch (in hardware)

I've been messing around with my own sort of development board for an Altera MAX 3064 because I have some downtime at w...

12 comments posted 20yrs

posted by brian.mcf1985

12 comments posted 20yrs posted by brian.mcf1985

XPS-Microblaze-Xilkernel

Hi All, I am a student of the University of Arizona. I am trying to get xilkernel to work with Microblaze on a spartan...

0 comments posted 20yrs

posted by ajaynair03

0 comments posted 20yrs posted by ajaynair03

FPGA interpolated FIR implementation

Hi everyone! I write here, after having googled for some days, because I'm looking for some advices. I'm working, for m...

0 comments posted 20yrs

posted by dario.locci

0 comments posted 20yrs posted by dario.locci

Simulation problem for the DDR controller

Hi, I am using the DDR controller(generated by MIG1.5) for the ddr MT46V32M16 -6 for the board V4MBlx60. I am getting t...

1 comments posted 20yrs

posted by subin.82

1 comments posted 20yrs posted by subin.82

Xilinx Virtex FPGA designers

I am working on behalf of a UK / Bristol based company - Clearspeed - www.clearspeed.com. They are looking for several...

0 comments posted 20yrs

posted by gallowayjames

0 comments posted 20yrs posted by gallowayjames

DDR Controller problems

Hi All, I'm trying to get a DDR controller fo r the Micron MT46V16M16TG-75 up and running on a Memec V2MB1000 dev board...

7 comments posted 20yrs

posted by simianfever

7 comments posted 20yrs posted by simianfever

How much time does it need to sort 1 million random 64-bit/32-bit integers?

Hi, Can I find a website that lists the time for sorting 1 million 64-bit/32-bit random data using the fastest software...

36 comments posted 20yrs

posted by wtxwtx

36 comments posted 20yrs posted by wtxwtx

Incorporating CoreGen files in EDK 8.1 peripheral

Hi folks, I have a problem and I need a clean solution: I created an OPB peipheral which includes AsyncFIFO (created wi...

4 comments posted 20yrs

posted by ales.gorkic

4 comments posted 20yrs posted by ales.gorkic

PLB master without xilinx ipif

Hi, Which is better --- to have plb master with xilinx ipif in it or without it? I want to avoid ipif but wanted to know...

2 comments posted 20yrs

posted by nitesh.guinde

2 comments posted 20yrs posted by nitesh.guinde

xilinx impact : usb failure

Hi groups, I got a spartan3E starter kit and have experienced trouble with usb jtag interface. While using Impact, usb...

0 comments posted 20yrs

posted by rponsard

0 comments posted 20yrs posted by rponsard

High Speed Serial MGTs using Aurora IP

Hi All, I'm trying to develop a serial link using the Aurora protocol between 2 MGT's on a V2pro FF672 based ML321 boar...

0 comments posted 20yrs

posted by bkamakot

0 comments posted 20yrs posted by bkamakot

EDK question - debugging PPC405 and MB..

Hi all, I would like to debug a system containing a microblze and a ppc405. I'm using the xmd (gdb) for both of these u...

0 comments posted 20yrs

posted by me_2003

0 comments posted 20yrs posted by me_2003