am working on a VIRETX-II FPGA and i am downloading the bit file by using the RBT File. i am now trying to decode a RBT file, i am so confused abt how the data are stored in those frames. i am not sure how the address of each frame and the column are written in the RBT.
arranged in frames..they do not match with description as said by xilinx.
I could say the same thing I said before: read the docu.
if multiply frames are loaded the the frame addr sub-fields autoincrement. The best thing is to generate a 'debug' bitstream' then each record contains each frame and you can see the frame addresses for each frame in sequence
thanx for the reply, i am using it for partial reconfiguration.
if i send the partially decoded file, with comments would you be able to help me a little bit more, though i have read those docs, i am kinda confused. i understand that multiple frames or the whole FPGA is being loaded.