PROBLEM: CPU memory bus is routed into FPGA, where memory-mapped registers are needed for accessing soft perhipherals. Memory bus is asynchronouse (i.e. EMIF).
I would create a table of registers, where the following parameters can be specified for each register.
REGISTER NAME WIDTH OFFSET FROM BASE ADDRESS ACCESS TYPE: R, W, R/W INTERNAL CLOCK NAME (assume bus I/F is async to this clock) WRITE STROBE GEN (sync'd to INTERNAL clock) READ STROBE GEN (sync'd to INTERNAL clock)
These register table would be the input to a code generator script/program which would output a VHDL file that has the bus interface on one side and the register in/out/sync signals on the back side.
I did something like this quite a few years ago, where the table was generated in MS Excel and the VHDL code generator was written in VBA for a serial (SPI-like) bus.
I could modify this, but I wondered if anyone knew of some script/code in the public domain which already does this. I would prefer something in perl, but any language would be acceptable.
If this doesn't exist, would anyone be interested in such a code generation tool. I'm more of a software hack, so my code isn't very pretty or pure. But, it works and is reasonably commented.
TIA
Urb