Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15255 Threads Posts
to

Worth reading in Field-Programmable Gate Arrays

uClinux on Virtex-4 Mini-Module

Hi Folks, Does anybody has any experience with uClinux running on Virtex4FX12 (ML403?) in PPC 405 processor. Can the LL...
7 comments posted 20yrs
posted by ales.gorkic
7 comments posted 20yrs posted by ales.gorkic

Issues w/ 8 lane Aurora sample design

Hi All, I'm trying to create a serial link operating at 2.5Gbps or higher using all 8 MGTs on the ML321 board. I modifi...
6 comments posted 20yrs
posted by bkamakot
6 comments posted 20yrs posted by bkamakot

FFT module with Virtex-4 xc4vlx15

Hi, I am having problems synthesizing the fft module generated for Virtex-4 xc4vlx15. The files generated are only for s...
0 comments posted 20yrs
posted by vivek.menon79
0 comments posted 20yrs posted by vivek.menon79

Virtex4 Rocket I/O. Power filtering.

Guys, I'm looking at using some MGT tiles in which just the transmitter is used. From the user guide:- Powering Unused...
3 comments posted 20yrs
posted by symon_brewer
3 comments posted 20yrs posted by symon_brewer

Xilkernel: Using the shared memory API

Hi peoples, This could be a stupid question and I sincerely hope not. I'm not a coder -- I'm a EE signal/systems kid wh...
1 comments posted 20yrs
posted by MKULTRA2
1 comments posted 20yrs posted by MKULTRA2

Calculate CRC in Virtex-Spartan II bitstream

Hi, I'm a student, I want calculate the CRC of a standard bitstream (Spartan II) Xilinx in C. I read xilinx's document(...
2 comments posted 20yrs
posted by verdicchio.francesco
2 comments posted 20yrs posted by verdicchio.francesco

Connecting two buses in Xilinx ISE

I am new to FPGA's and am designing my first circuit in Xilinx ISE. I have two 'building block' symbols on my schematic...
1 comments posted 20yrs
posted by nevo_n
1 comments posted 20yrs posted by nevo_n

impact.log files

Hi, Our latest prototype board doesnt produce any output and even a simple module to output '1's and '0's on some pins...
2 comments posted 20yrs
posted by subhasri.krishnan
2 comments posted 20yrs posted by subhasri.krishnan

Correlator block

Hi, I am trying to implement a correlator block in a Virtex-4 FPGA. This FPGA is connected to an ADC08D1500 chip and th...
1 comments posted 20yrs
posted by vivek.menon79
1 comments posted 20yrs posted by vivek.menon79

Soft processor performance

I see that Xilinx claim 0.92 Dhrystone 2.1 mips/Mhz for Microblaze and Altera varously up to 1.2 dmips/Mhz. Does anyone...
1 comments posted 20yrs
posted by baboonspanker
1 comments posted 20yrs posted by baboonspanker

EDK Using External Ports to toggle FPGA pins

Hello All, I am having a hard time understanding EDK ---> FPGA tool flow (I think). I am using EDK/ISE 8.1, testing the...
4 comments posted 20yrs
posted by kyle.hable
4 comments posted 20yrs posted by kyle.hable

Xilinx Corgen & Synplicity... Anyone? Help?

Hey all, Thanx in advance for any help. I've got a few FIFO cores that I created in Xilinx Core Generator. I instantiat...
2 comments posted 20yrs
posted by pauljbennett
2 comments posted 20yrs posted by pauljbennett