Field-Programmable Gate Arrays

Issues w/ 8 lane Aurora sample design

Hi All, I'm trying to create a serial link operating at 2.5Gbps or higher using all 8 MGTs on the ML321 board. I modifi...

6 comments posted 20yrs

posted by bkamakot

6 comments posted 20yrs posted by bkamakot

Clock signal remains HIGH forever in Spartan-3 Starter Kit from Digilent

Hi, I have a problem with my Spartan-3 Starter Board from Digilent (FPGA xc3s400-5ft256). The clock (at pin T9) is alwa...

1 comments posted 20yrs

posted by javier.valcarce

1 comments posted 20yrs posted by javier.valcarce

FFT module with Virtex-4 xc4vlx15

Hi, I am having problems synthesizing the fft module generated for Virtex-4 xc4vlx15. The files generated are only for s...

0 comments posted 20yrs

posted by vivek.menon79

0 comments posted 20yrs posted by vivek.menon79

Virtex4 Rocket I/O. Power filtering.

Guys, I'm looking at using some MGT tiles in which just the transmitter is used. From the user guide:- Powering Unused...

3 comments posted 20yrs

posted by symon_brewer

3 comments posted 20yrs posted by symon_brewer

2Khz clock signal from 50Hz main frequency with ADPLL

Hello everyone, I would like to ask if it is possible to generate 2Khz clock signal from 50Hz main frequency using an A...

21 comments posted 20yrs

posted by rasit.sahin

21 comments posted 20yrs posted by rasit.sahin

Xilkernel: Using the shared memory API

Hi peoples, This could be a stupid question and I sincerely hope not. I'm not a coder -- I'm a EE signal/systems kid wh...

1 comments posted 20yrs

posted by MKULTRA2

1 comments posted 20yrs posted by MKULTRA2

Calculate CRC in Virtex-Spartan II bitstream

Hi, I'm a student, I want calculate the CRC of a standard bitstream (Spartan II) Xilinx in C. I read xilinx's document(...

2 comments posted 20yrs

posted by verdicchio.francesco

2 comments posted 20yrs posted by verdicchio.francesco

EDK + Assembly Output Files + External Memory Usage

Hi Gurus, I am new to EDK and embedded software please help me... I am trying some example and test applications using...

4 comments posted 20yrs

posted by vlsi_kida

4 comments posted 20yrs posted by vlsi_kida

Connecting two buses in Xilinx ISE

I am new to FPGA's and am designing my first circuit in Xilinx ISE. I have two 'building block' symbols on my schematic...

1 comments posted 20yrs

posted by nevo_n

1 comments posted 20yrs posted by nevo_n

impact.log files

Hi, Our latest prototype board doesnt produce any output and even a simple module to output '1's and '0's on some pins...

2 comments posted 20yrs

posted by subhasri.krishnan

2 comments posted 20yrs posted by subhasri.krishnan

Correlator block

Hi, I am trying to implement a correlator block in a Virtex-4 FPGA. This FPGA is connected to an ADC08D1500 chip and th...

1 comments posted 20yrs

posted by vivek.menon79

1 comments posted 20yrs posted by vivek.menon79

Soft processor performance

I see that Xilinx claim 0.92 Dhrystone 2.1 mips/Mhz for Microblaze and Altera varously up to 1.2 dmips/Mhz. Does anyone...

1 comments posted 20yrs

posted by baboonspanker

1 comments posted 20yrs posted by baboonspanker

EDK Using External Ports to toggle FPGA pins

Hello All, I am having a hard time understanding EDK ---> FPGA tool flow (I think). I am using EDK/ISE 8.1, testing the...

4 comments posted 20yrs

posted by kyle.hable

4 comments posted 20yrs posted by kyle.hable

Xilinx Corgen & Synplicity... Anyone? Help?

Hey all, Thanx in advance for any help. I've got a few FIFO cores that I created in Xilinx Core Generator. I instantiat...

2 comments posted 20yrs

posted by pauljbennett

2 comments posted 20yrs posted by pauljbennett

chipscope opb monitor

I try to use the opb/iba unit of chipscope to monitor the opb bus within a simple edk design. I took the chipscope lab...

5 comments posted 20yrs

posted by someone

5 comments posted 20yrs posted by someone