Field-Programmable Gate Arrays

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Re: Free VHDL or Verilog Simulator

>Hi, > >Altera's Quartus II does not include a free simulator. Is there >a free VHDL or Verilog simulator that is reaso...
1 comments posted 11yrs
posted by 93490
1 comments posted 11yrs posted by 93490

Functional safety guidelines

Hello, I wonder maybe someone have automotive functional safety guidelines for VHDL and is willing to share? I think th...
2 comments posted 11yrs
posted by mailsoc
2 comments posted 11yrs posted by mailsoc

wrong waveforms in vivado waveform viewer

Has anyone experience the Vivado waveform viewer just making up waveforms? I have a module with two different signals,...
1 comments posted 11yrs
posted by langwadt
1 comments posted 11yrs posted by langwadt

Bidirectional Pin FPGA (Parallel ADC)

Hey guys(and gals) FPGA convert here trying to use bidirectional pins on an Altera Board within a data acquisition proje...
9 comments posted 11yrs
posted by osodipe
9 comments posted 11yrs posted by osodipe

xc3sprog "instruction capture is 0x3f" (solved)

Hi, if anybody else runs into the same problem with an FPGA module: xc3sprog failed to upload the bitstream to a Sparta...
2 comments posted 11yrs
posted by 24789
2 comments posted 11yrs posted by 24789

calculations of logic vectors and constant

what is the prefered option of arithmetic operations using logic vectors and constant? convert logic vector to integer...
2 comments posted 11yrs
posted by 101236
2 comments posted 11yrs posted by 101236

ZPU-based SoC for Numato Saturn board with DRAM

Hi, this is a "public backup" of a holiday project maybe it's of use to someone: https://drive.google.com/file/d/0B1gLU...
0 comments posted 11yrs
posted by 24789
0 comments posted 11yrs posted by 24789

Has anyone forked any Xilinx IP?

What is the "recommended" way to do IP forking from Xilinx's repos? Not for public distribution but to have a modified...
4 comments posted 11yrs
posted by sp
4 comments posted 11yrs posted by sp

LVDS problem - Black magic anyone?

I have an LVDS related issue that drives me crazy: There are two boards with a FPGA that are connected by a ca. 30cm ca...
13 comments posted 11yrs
posted by thomas.entner99
13 comments posted 11yrs posted by thomas.entner99

Basic question: sequence of execution within FPGAs

Trying to get my head around FPGAs after 40 years of 2GLs. I can't seem to find a clear exposition of the following, wo...
10 comments posted 11yrs
posted by Bruce Varley
10 comments posted 11yrs posted by Bruce Varley

multicycle path - synplify pro

Hi everyone, I'm experiencing an issue with Synplify Pro E-2010.09A-1. I have to insert some multicycle paths in order...
2 comments posted 11yrs
posted by al.basili
2 comments posted 11yrs posted by al.basili

strange effect with tristate output

I'm using a XC95144XL, two pins are an input for a 5V signal, which have pullup resistors (3k3). Setting the pins to lo...
4 comments posted 11yrs
posted by fb
4 comments posted 11yrs posted by fb