Hi, I read a job post which requires:
High-speed SERDES interfacing such as PCIe, SDI, SGMII, XAUI
I know FPGA vendors have PCIe IP interfaces. What is the job content with the above statements? It requires the engineer to design a PCIe, SDI, SGMII and XAUI interfaces in house? Or it can accept to use third party IP?
Thanks for explain it to me.
the
nd XAUI
This is probably a case of "if you have to ask you don't have the experienc e".
Using the question as a search term in Google turns up a job posting for Cr eston looking for people with Xilinx or Altera experience as the first bull et item, so this likely means that you have actual experience use the MGT, Multi-Gigabit Transceivers, in a real world project implementing one or mor e of the listed protocols.
Ed McGettigan
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