Latest threads in Field-Programmable Gate Arrays

strange effect with tristate output

I'm using a XC95144XL, two pins are an input for a 5V signal, which have pullup resistors (3k3). Setting the pins to lo...

4 12yrs

fb

4 12yrs fb

How can Spartan-6 interface with 10/100 Mb/s Ethernet?

Hi, I read LogiCORE IP AXI Ethernet Lite MAC (v1.01.b), which says that the Ethernet interface is with 10Mb/s 100Mb/s....

2 12yrs

rxjwg98

2 12yrs rxjwg98

Could you give me an example on synthesis techniques?

Hi, I read a paper on FPGA design. It has the following statements: "Successfully simulated programs might not work on...

3 12yrs

rxjwg98

3 12yrs rxjwg98

floating point synthesis on Xilinx FPGAs using ISE Webpack

Hi I have been researching floating and/or fixed point support for Xilinx FPGAs that can be synthesized using the ISE W...

3 12yrs

walburn

3 12yrs walburn

Professional VHDL Examples?

Over the years I have taught myself Verilog and VHDL, and although I am qui te comfortable with Verilog, I feel as thou...

8 12yrs

wabac0

8 12yrs wabac0

icse syllabus

Central books online is a online Central books , icse syllabus online is a book store which provides you icse books for...

0 12yrs

raghucbsc

0 12yrs raghucbsc

Primitive debuggable UART interface to a Nios within a multi-Nios system

I am working on an IP core with a Nios controller. This IP will eventually be integrated into a multi-Nios system. I al...

19 12yrs

azhiping

19 12yrs azhiping

Know any good public FPGA projects to contribute to?

Hi all, Can you suggest any good FPGA projects I could contribute to? I have some free time and want to work on somethi...

22 12yrs

junkemail543212345

22 12yrs junkemail543212345

Generating a desired synthesizable binary pulse train on FPGA using VHDL

Hello Everyone I am new to VHDL programming and FPGA. I have a Virtex - 4 FPGA and I wish to generate a binary pulse tr...

18 12yrs

100919

18 12yrs 100919

CFP: EECEA2014 Malaysia

The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Asia P...

0 12yrs

hazel.sdiwc

0 12yrs hazel.sdiwc

CFP: The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Malaysia

The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Asia P...

0 12yrs

hazel.sdiwc

0 12yrs hazel.sdiwc

vmWare supporting Avnet Virtex-5 PCIe board

Hi, I am planning to install vmWare on one of my server machines and create virtual servers on it. I need to access a V...

1 12yrs

sheikh.m.farhan

1 12yrs sheikh.m.farhan

Help with Address load logic

Hi, I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all th e data samples from the ADC and another...

7 12yrs

syed.huq.a

7 12yrs syed.huq.a

Perl + Xilinx + commandline = Module::Build::Xilinx

Hello I have released Module::Build::Xilinx (currently at version 0.05) to CPAN. (https://metacpan.org/pod/Module::Buil...

4 12yrs

walburn

4 12yrs walburn

Using FPGA as dual ported ram

To interface a fast sampling ADC to a CPU I'm considering to use a fifo or dual ported ram and a small controlling CPLD...

29 12yrs

stef33d

29 12yrs stef33d

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