Field-Programmable Gate Arrays

Could you give me an example on synthesis techniques?

Hi, I read a paper on FPGA design. It has the following statements: "Successfully simulated programs might not work on...

3 comments posted 12yrs

posted by rxjwg98

3 comments posted 12yrs posted by rxjwg98

floating point synthesis on Xilinx FPGAs using ISE Webpack

Hi I have been researching floating and/or fixed point support for Xilinx FPGAs that can be synthesized using the ISE W...

3 comments posted 12yrs

posted by walburn

3 comments posted 12yrs posted by walburn

Professional VHDL Examples?

Over the years I have taught myself Verilog and VHDL, and although I am qui te comfortable with Verilog, I feel as thou...

8 comments posted 12yrs

posted by wabac0

8 comments posted 12yrs posted by wabac0

icse syllabus

Central books online is a online Central books , icse syllabus online is a book store which provides you icse books for...

0 comments posted 12yrs

posted by raghucbsc

0 comments posted 12yrs posted by raghucbsc

Primitive debuggable UART interface to a Nios within a multi-Nios system

I am working on an IP core with a Nios controller. This IP will eventually be integrated into a multi-Nios system. I al...

19 comments posted 12yrs

posted by azhiping

19 comments posted 12yrs posted by azhiping

Know any good public FPGA projects to contribute to?

Hi all, Can you suggest any good FPGA projects I could contribute to? I have some free time and want to work on somethi...

22 comments posted 12yrs

posted by junkemail543212345

22 comments posted 12yrs posted by junkemail543212345

Generating a desired synthesizable binary pulse train on FPGA using VHDL

Hello Everyone I am new to VHDL programming and FPGA. I have a Virtex - 4 FPGA and I wish to generate a binary pulse tr...

18 comments posted 12yrs

posted by 100919

18 comments posted 12yrs posted by 100919

CFP: EECEA2014 Malaysia

The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Asia P...

0 comments posted 12yrs

posted by hazel.sdiwc

0 comments posted 12yrs posted by hazel.sdiwc

CFP: The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Malaysia

The International Conference on Electrical, Electronics, Computer Engineering and their Applications (EECEA2014) Asia P...

0 comments posted 12yrs

posted by hazel.sdiwc

0 comments posted 12yrs posted by hazel.sdiwc

vmWare supporting Avnet Virtex-5 PCIe board

Hi, I am planning to install vmWare on one of my server machines and create virtual servers on it. I need to access a V...

1 comments posted 12yrs

posted by sheikh.m.farhan

1 comments posted 12yrs posted by sheikh.m.farhan

Help with Address load logic

Hi, I'm trying to implement a trigger with 2 BRAMs with one BRAM storing all th e data samples from the ADC and another...

7 comments posted 12yrs

posted by syed.huq.a

7 comments posted 12yrs posted by syed.huq.a

Perl + Xilinx + commandline = Module::Build::Xilinx

Hello I have released Module::Build::Xilinx (currently at version 0.05) to CPAN. (https://metacpan.org/pod/Module::Buil...

4 comments posted 12yrs

posted by walburn

4 comments posted 12yrs posted by walburn

Using FPGA as dual ported ram

To interface a fast sampling ADC to a CPU I'm considering to use a fifo or dual ported ram and a small controlling CPLD...

29 comments posted 12yrs

posted by stef33d

29 comments posted 12yrs posted by stef33d

wishbone bus between two fpgas

Hi everyone, we are in the preliminary phase of the architecture definition for our system and we estimated FPGA resour...

4 comments posted 12yrs

posted by al.basili

4 comments posted 12yrs posted by al.basili

ECP5 support in Latest Diamond 3.2 IDE from Lattice ( 64-bit Linux version) ?

I have downloaded latest Diamond and installed it on my Gentoo OS. It works normally except that I can't choose ECP5 pa...

16 comments posted 12yrs

posted by brankob

16 comments posted 12yrs posted by brankob