Davies-meyer in VHDL

Hi everybody;

I am new in VDHL and crypto also. I would like to implement the Davies-meyer HASH function ( Hi = Emi(Hi-1)+Hi-1 ) in VHDL. The problem I am having is that: The block cipher I am having (Kasumi) have 64 bits input and output and the HASH function(SHA1) is having 160 bits output. I don't know how can I manage an agrement between them in order to implement the Davies-meyer. Can anyone help me in getting an arrangement of those functions or indicate where I can find literatures or implementations about this. Thanks all and nice day. Adam.

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