Field-Programmable Gate Arrays

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September training?

We have been encouraged to spend some of our remaining training budget by taking a week-long seminar in September. I am...
8 comments posted 20yrs
posted by pomerado
8 comments posted 20yrs posted by pomerado

Undergrad project-8051 specifications??

Hi all. I'm an undergrad student doing a year long project on designing an 8051 variant for FPGA. We're required to dec...
6 comments posted 20yrs
posted by neha.karanjkar
6 comments posted 20yrs posted by neha.karanjkar

How to load the data off the FPGA to the PC?

I am testing my design on Xilinx ML402 board. I can send data from the PC to the FPGA board through the parallel port u...
2 comments posted 20yrs
posted by maricic
2 comments posted 20yrs posted by maricic

Actel Fusion?

Has anyone here had any experiance with the Actel Fusion FPGAs? I saw a couple of posts asking this about 6 months ago,...
2 comments posted 20yrs
posted by mmdst23
2 comments posted 20yrs posted by mmdst23

Semi-OT: Free (USA) tube of Philips CPLDs

Amongst my junk I found a tube of 25 PZ5032CS10A44 32-macrocell CPLDs in PLCC44 package. Datasheet at You pay postage, y...
0 comments posted 20yrs
posted by zwsdotcom
0 comments posted 20yrs posted by zwsdotcom

Question on Virtex-4 CLB

If I look in the FPGA editor there seems to be one element in the CLB of a Virtex-4 that is odd as compared to previous...
10 comments posted 20yrs
posted by ehliar
10 comments posted 20yrs posted by ehliar

EDK 6.3 project file growth

Hi ... I had an EDK project which took longer and longer to load. In the begining this was tolerable as there were not...
1 comments posted 20yrs
posted by MSchoeberl
1 comments posted 20yrs posted by MSchoeberl

synchronisation on rising and falling edges

Hello, I have a little problem and I need some help. I program a controller for a DDR-SDRAM on a FPGA-Board (Virtex 4,...
2 comments posted 20yrs
posted by "kunz2.10.Hinz"
2 comments posted 20yrs posted by "kunz2.10.Hinz"

Spartan-4 ?

New low cost families other than from Xilinx are known to be coming this autumn (Cyclone-3, MAX3, LatticeXP2) but there...
17 comments posted 20yrs
posted by Antti.Lukats
17 comments posted 20yrs posted by Antti.Lukats

FFT IP CORE: XK_INDEX???

When I use the xfft2.0 core to simulate a 1024_point FFT by the ModelSim. Why does the FFT's behavioral simulation fail...
0 comments posted 20yrs
posted by zyl-02042101
0 comments posted 20yrs posted by zyl-02042101

FFT : XK_INDEX

From the wave, I find the start,rfd,busy,edone,done and the dv are the same as the datesheet shown, but the xk_index is...
0 comments posted 20yrs
posted by zyl-02042101
0 comments posted 20yrs posted by zyl-02042101

FSL read/write problems

Hi all, I'm trying to implement a correlator as a coprocessor on the FSL bus. The first thing I've done is generate the...
6 comments posted 20yrs
posted by simianfever
6 comments posted 20yrs posted by simianfever

Spartan 3 and 5V input

Newbie alert... I would like to drive my Spartan 3 design with inputs from a 5V source. I've been unable to find anythi...
7 comments posted 20yrs
posted by nevo_n
7 comments posted 20yrs posted by nevo_n