I have a little problem and I need some help.
I program a controller for a DDR-SDRAM on a FPGA-Board (Virtex 4, Xilinx).
For the synchronisation signal I need a process that is case sensitiv on both edges.
But the following commands are not synthesizeable:
" if DQS'event then..."
" if (DQS'event and DQS = '1') and (DQS'event and DQS = '0') then..."
THx for any help...