synchronisation on rising and falling edges


I have a little problem and I need some help.

I program a controller for a DDR-SDRAM on a FPGA-Board (Virtex 4, Xilinx).

For the synchronisation signal I need a process that is case sensitiv on both edges.

But the following commands are not synthesizeable:

" if DQS'event then..."


" if (DQS'event and DQS = '1') and (DQS'event and DQS = '0') then..."

THx for any help...

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You need to instanciate the DDR IOB flip flop by hand, you can't infer them from VHDL. Look at the templates in ISE for examples.

And btw, are you gonna drive directly the IOB FF clk input from the DQS signals ???

Hum ... the logic reduction of the condition you put is "if false then" ...


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Sylvain Munaut

Synplicity can infer DDR IOB input registers, but there are two outputs, one for each clock.

If you need DDR functionality inside the FPGA (not in the IOBs), the only way I know of is two roll your own DDR flop from two SDR flops and

3 xor gates:

ddr: process (clk, rst) is variable qr, qf : std_logic; begin if rst = '1' then qr := '0'; qf := '0'; elsif rising_edge(clk) then qr := d xor qf; elsif falling_edge(clk) then qf := d xor qr; end if; q I program a controller for a DDR-SDRAM on a FPGA-Board (Virtex 4, Xilinx).

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