Field-Programmable Gate Arrays

xilinx platform studio 7.1i

Hi, does anyone have any experience of using xilinx platform studio with the following characteristics 1) microblazed b...

0 comments posted 19yrs

posted by chrisdekoh

0 comments posted 19yrs posted by chrisdekoh

removing Ethernet_MAC kills mini-module project

I have a memec mini-module board. I've loaded and run the reference design and I am able to boot all the way into the L...

2 comments posted 19yrs

posted by someone

2 comments posted 19yrs posted by someone

Xilinx Platform Studio, build up System: "block-RAM components require the adjacent multiplier"

Hi, after Developing connection my custom peripheral to the OPB-Bus, I tried to download my Design to the FPGA. The cus...

6 comments posted 19yrs

posted by peter.kampmann

6 comments posted 19yrs posted by peter.kampmann

SoC Development Board

In the company I'm working for we're using DSPs and FPGAs to develop motion controllers. Since we're doing all the posi...

7 comments posted 19yrs

posted by markus

7 comments posted 19yrs posted by markus

Clock Source in Low Latency Mode RocketIO

Hi everyone! I have a uncertainty concerning clock source using the Virtex 4 RocketIOs. I would like to use them in red...

0 comments posted 19yrs

posted by Michael.Niegl

0 comments posted 19yrs posted by Michael.Niegl

EDK8.2: bidirectional signals when top-level is ISE

I've just upgraded to 8.2 ISE and EDK and my project doesn't synthesize anymore. It complaints about not finding x_O,x...

1 comments posted 19yrs

posted by mbmsv

1 comments posted 19yrs posted by mbmsv

Xilinx ISE 8.2 Problem

Its not a big problem but annoying nonetheless. I installed the ISE 8.2 last week and have been using the view rtl sche...

0 comments posted 19yrs

posted by colinhankins

0 comments posted 19yrs posted by colinhankins

use of Barrel shifter IN ARM TDMI 9

i am preparing for intervew and i want the answer how Barrel shifter can be used to optimize of C code at ARM processor...

2 comments posted 19yrs

posted by karunesh.ind

2 comments posted 19yrs posted by karunesh.ind

Opencores mem_ctrl

Does anyone have any expereince/opinions with the mem_ctrl project in opencores? http://www.opencores.org/projects.cgi/w...

0 comments posted 19yrs

posted by karrelsj

0 comments posted 19yrs posted by karrelsj

Cmult in System Gnerator

Hi, We are designing a linear phase FIR filter. Several Cmults are included in the FIR filter as multipliers. All the c...

0 comments posted 19yrs

posted by kuan.zhou

0 comments posted 19yrs posted by kuan.zhou

Spartan-3: 5V -> 2.5V level shifting

Hi, I would like to configure a spartan-3 FPGA with an 5V CMOS microcontroller. I have read xilinx database answer rega...

16 comments posted 19yrs

posted by jidan1

16 comments posted 19yrs posted by jidan1

Xilkernel: Problem with mutex

Hello, i have created a fairly simple Microblaze-based system, just one core, opb-UART, BRAM, opb-timer and opb-intc. I...

10 comments posted 19yrs

posted by ahofmann

10 comments posted 19yrs posted by ahofmann

problems with viewdraw

Hi Group Im having problems with viewdraw schematic for VHDL. Im building a system with lots of modules, so Im using th...

0 comments posted 19yrs

posted by brian.rasmussen80

0 comments posted 19yrs posted by brian.rasmussen80

Help for Altera Nios II Cyclone EP1C12 evaluation kit!

Hello out there! I have purchased an Altera Nios II Cyclone based (EP1C12F324) evalution kit a while ago and didn't get...

2 comments posted 19yrs

posted by zkcmbcyk9

2 comments posted 19yrs posted by zkcmbcyk9

Linear Interploation Algorithms

Hi, I was wondering what is most fast and efficient intepolation algorithm that easily adaptable in a Spartan 3 and abl...

9 comments posted 19yrs

posted by eziggurat

9 comments posted 19yrs posted by eziggurat