Spartan-3: 5V -> 2.5V level shifting

I would use 1 kilohm. No need to push more current than necessary. Regarding 2: You quote worst-case numbers that assum lowest Vcc on the FPGA and higest possible Vcc on the uP. Keep the FPGA fed with at least 3.2 V, and you will see that same voltage on the output (this is CMOS !), and keep the uP Vcc slightly below 5V. But you will not have much noise immunity. Peter Alfke

jidan,

Peter makes a good point: if the resistance is too low, then you are injecting current into the 2.5 V supply, and it may begin to drift up, and out of regulation.

One way to avoid that, and to avoid any rail supply being driven above its intended output, is to balance the injected current with a simple resistor across the power supply, present all the time.

So, if you think you will inject 100 mA worst case into the 2.5V rail, then plan on having a load of at least 100 mA on the 2.5 volt supply. If the 2.5 volt supply has a minimum normal load of 50 mA, then you will need an additional 50 mA load, just in case. 2.5V/.05=50 ohms (51 ohms, nearest 5% value).

All this because regulators are good at regulating a load, but incapable of regulating when you source current into there output terminal.

Aust> snipped-for-privacy@hotmail.com wrote:

Thank you Austin and Peter for you replies.

I still have 2 questions

2)Why use a parralell resistor to the voltage regulator and waste power to handle the reverse current. Why not just add a reverse biased schotkey diode from the output to the input of the voltage regulator?

Austin Lesea schrieb:

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Answers below,

Aust> Thank you Austin and Peter for you replies.

The value is up to you: the choice is for speed, signal integrity, etc. Fast would be the smallest value, slower is a larger value. Peter's point is that if this is a slow interface (usually is), you don't need low resistance.

We are not interested in protecting the regulator. What if the current forces the 2.5V Vcco and Vccaux to 5 volts? The the chip blows up...

The resistor value is a compromise between speed and current forced into the pin. The driver output impedance is probably below 10 Ohm. With a total load capacitance of 30 pF that creates an output time constant of 300 ps, pretty fast. With a 1 kilohm resistor directly attached to the FPGA pin, that pin has a capacitance of 10 pF. Times 1 kilohm that is a time constant of

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yes,

Use the largest value that works, and you can also parallel a small C. That's what the universal programmers do, for wide pin voltage compliance, and keeps the edges fast enough to avoid problems.

Or, you can use a DDR regulator : they are designed for source and sink. (if you expect a lot of unknown injection effects, tho worrying about mA in a Spartan-3 design is a little ?? )

-jg

Jim,

DDR regulator? I must have missed this new term.

Do you have an example?|

Asutin

Another solution if you are worried about power consumption is a humble $.14 TL431 shunt regulator - good for up to 100 mA. We use this on some of our designs (on Spartan 2, making sure the the 3.3v rail doesnt get pulled up too high by 5V pullups on I/O pins) I'd set the TL431 for about 2.75V on the 2.5V rail...

Peter Wallace

Sure, Go to Linear or Maxim's web sites, and search for DDR regulator. These target the Vtt terminations on DDR memory busses, and they can source and sink current.

-jg

Be cautious while working with CCLK configuration pin. Our experience: for +3.3v CMOS driver serial resistor to that pin should be no more than 100 ohm. Otherwise configuration clock CCLK doesn't work. I highly recommend to read XAPP453 "The 3.3V Configuration of Spartan-3 FPGAs":

It seems to me that 100 ohm required for proper "zero" level translating to CCLK pin (at least it looks so on oscilloscope). If it's true, this can lead to failure with Rser=220OHM. I recommend to use for level shifting simple gate logic, for example SN74LVC3G17.

Another example is the LP2996 which we use on our development boards.

John Adair Enterpo> Aust>

Jim,

Thanks. I remember back when Virtex first offered SSTL and HSTL we had to look around for devices that did this. I am happy to see a whole line of components spring up to support termination voltage busses.

We certainly were not first with SSTL and HSTL interfaces, but 9 years ago it just had not taken off yet, I suspect.

The term DDR regulator seems to have come from DDR-SRAM being the number one reason to need a regulator that can both source, and sink current.

Austin

Jim Granville wrote:

Thanks all for your replies. Peter, Austin,

I will be using voltage regualtors from national semiconducter and so I posted my question to one of the national engineers. I posted a quoted passage from xilinx database answer which says that xilinx recommends a parallel resistor for power regualtion purposes. He recommended using a diode rather than a parallel resistor and he doesnt understand why xilinx prefers using a parallel resistor, although a diode is more power efficient. You can read our conversition here:

Peter Alfke schrieb:

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I'm not sure that you get what is going on with the parallel resistor. When the input is driven above the rated voltage of the input, the clamp diodes pass current to the Vccio pin. This current should not be allowed to flow back to the power converter, not because it may damage the power converter, but because a rise in the Vccio voltage may damage the FPGA. Adding a diode across the regulator only clamps the voltage to the INPUT voltage of the regulator and depending on that voltage level may not protect the FPGA at all. Xilinx has no way of knowing what voltage you are feeding to your voltage regulator input, so they can't recommend the parallel diode as a general method of dealing with this current from the IOs.

If the diode works for your design with your regulator voltages, then you should be ok. But be sure to check the voltages all around and that it will not exceed any of the ratings on the FPGA or the regulator.

BTW, what happens to the input voltage to the regulator if current flows back to that input? The current ultimately has to find a path to ground. If the input source can not handle the reverse current then you have not solved the problem.

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JJ, most voltage regulator can only drive current into the load. They cannot regulate the voltage when the current flows"backwards" into the regulator. (But, as mentioned, there are some "DDR" regulators that can source and sink,)

Yhe National guy looked at this as a regulator protection question, and answered accordingly. He did not understand the real issue, that we need to prevent the regulator output from going higher than specified, even when the current is reversed.

The primitive cure is a bleed> Thanks all for your replies.

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