Hi, does anyone have any experience of using xilinx platform studio with the following characteristics
1) microblazed based platform
2) one of the peripherals exists only in edif format, as this block was built using handel C previously (thus I have create the necessary mpd files and bbd files in the data directory of the pcores//data directory
how to do VHDL behavioral simulation with such a scenario using modelsim in such a case? does anyone have any example or any knowhow on how to do this?
thanks! Christopher