Hi everyone!
I have a uncertainty concerning clock source using the Virtex 4 RocketIOs. I would like to use them in reduced latency mode "Full PCS Bypass". In the user guide it says for this mode the RXUSRCLK has to be derived internally from RXUSRCLK2 (clocking the interface to the fabric) through internal dividers. In the 4 byte interface mode I plan to use the ratio between RXUSRCLK and RXUSRCLK2 is 1:1 though. This makes me wonder, if it is possible, to source RXUSRCLK2 externally (this isn't explicitly stated anywhere in the guide). This is an absolute must for my design as there is no way to recover a clock from the incoming data signal.
Maybe someone can help me clarify this problem.
Cheers, Michael