Field-Programmable Gate Arrays

Nios II dev board

Hi everybody, I started to develop my fir filter with Quartus and Nios II dev board, with an Altera Stratix II EP2S60ES...

0 comments posted 19yrs

posted by dario.locci

0 comments posted 19yrs posted by dario.locci

How to oerform a functional simulation of a QuartusII design with Modelsim?

Hi All, we are having troubles in simulating our design with QuartusII. We found that the QuartusII simulator is dramat...

0 comments posted 19yrs

posted by Totti10

0 comments posted 19yrs posted by Totti10

ISE DDR Memory Controller to write between RAM and FPGA

I need help on how to use the EDK DDR memory controller in ISE to write to/from ram and fpga directly. I have implement...

4 comments posted 19yrs

posted by akcooper8

4 comments posted 19yrs posted by akcooper8

System Generator implement to FPGA problem

Hi, I have two problems about the FPGA implementation after I finished my design with Xilinx block set in Matlab. 1. Wh...

1 comments posted 19yrs

posted by yifei.luo

1 comments posted 19yrs posted by yifei.luo

ddr2 sodimm controller

Hi! i am having problem to communicate between virtex4 fx60 to 512 SODIMM. I use the MIG1.6 to generate a controller. I...

5 comments posted 19yrs

posted by waishanl

5 comments posted 19yrs posted by waishanl

QED files

Hi, I'm looking for the two QED's accessory files: qed_filt.c qed_cgen.h Can you help me? Thanks, Roberto -- "Malo ho'o...

0 comments posted 19yrs

posted by iz5fcy_NOSPAMPLEASE

0 comments posted 19yrs posted by iz5fcy_NOSPAMPLEASE

Virtex-5: small little things.

Xilinx isnt advertizing 'small things' that are also coming as bonus with Virtex-5, I found one by accident while brows...

3 comments posted 19yrs

posted by Antti.Lukats

3 comments posted 19yrs posted by Antti.Lukats

Is it worth learning SOPC Builder, DSP Builder & Nios Processor?

Hello, I've been seeing more training at Altera concerning their SOPC Builder, DSP Builder & the Nios Processor so I wa...

5 comments posted 19yrs

posted by jjlindula

5 comments posted 19yrs posted by jjlindula

Anyone had success with MIG, DDR2 and V2Pro?

Hi We are planning to use MIG to generate a DDR2 interface for a V2Pro30 design, but I'd like to know if anyone has don...

3 comments posted 19yrs

posted by gwatson

3 comments posted 19yrs posted by gwatson

windows xp networking, please help?

i have three windows xp computers one xp home laptop one pro desktop and another pro desktop which acts as a print serv...

3 comments posted 19yrs

posted by boystrosboy

3 comments posted 19yrs posted by boystrosboy

Max Plus II and Synthesis issues

Has anyone had any luck importing the EDIF output of the " MAX+PLUS II Advanced Synthesis Tool" into Max Plus II? I hav...

0 comments posted 19yrs

posted by mmdst23

0 comments posted 19yrs posted by mmdst23

MicroBlaze : Linkerscript for splitting the text block into 64kByte blocks

Hi all, I am implementing a microblaze processor in a subdesign in a Virtex4 component (ISE v7.1 sp3, EDK v7.1 sp2). Th...

3 comments posted 19yrs

posted by zeemanbe

3 comments posted 19yrs posted by zeemanbe

Driving a 30 bit wide LVTTL bus at 160MHz

Hello, In my future design I could win a lot of pins if I could drive a bus at 160MHz. Because of bank restrictions and...

6 comments posted 19yrs

posted by Karel.Deprez

6 comments posted 19yrs posted by Karel.Deprez

Addressing DDR-RAM

Hello, I've got a Xilinx Virtex 4 FPGA and would like to address the onboard DDR-SDRAM. I've found out that I can insta...

2 comments posted 19yrs

posted by "Thomas.10.Hinz"

2 comments posted 19yrs posted by "Thomas.10.Hinz"

Simlex in VHDL/FPGA

Hi I'm need to implement a simplex linear programming solution in an FPGA/VHDL. The object is to take blocks of data sa...

0 comments posted 19yrs

posted by Fougueux

0 comments posted 19yrs posted by Fougueux