Has anyone had any luck importing the EDIF output of the " MAX+PLUS II Advanced Synthesis Tool" into Max Plus II? I have a bunch of VHDL modules, and I need to tie them with a megawizard output file at the top level, so I thought it would be easier to do that part graphicly, and create a symbol for my top-level VHDL design. I've been getting compile errors in the EDIF that don't make sense, like "can't open file*.lmf" and "can't find design file 's_dffe'". Does anyone have any suggestions?
I'm working on a design targeted at board we designed and built in-house about 5 or so years ago, and it has a variant of a Flex10KE that isn't supported by Quartus II. Someone at Altera suggested trying to target a simular device, and changing the name in the programming file, which *might* work, but I want to get at least this part of the design working in Max Plus II as well, so if it dosen't work from Quartus I can tell if it's a design bug, or a tools issue.
Everyone else here has, as far as I know, worked with only block diagram designs in Max Plus II, so they haven't had this issue.