Field-Programmable Gate Arrays

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Static Power vs. Temperature

Hi, Hope everyone is doing fine. I'm trying to estimate static power consumption of my system in higher temperature. I'...
2 comments posted 20yrs
posted by amirhossein.gholamipour
2 comments posted 20yrs posted by amirhossein.gholamipour

pin name misspelling error!

Hi, Hi, I am getting the following error when I create a peripheral of my own and then add it to the project. As you ca...
1 comments posted 20yrs
posted by vbhanu
1 comments posted 20yrs posted by vbhanu

Xilinx ISE ucf management

Is there any way to switch from a ucf file for an ML402 dev board to a ucf file for a ML403 board without having to del...
4 comments posted 20yrs
posted by bradsmallridge
4 comments posted 20yrs posted by bradsmallridge

Non deterministic behaviour in quartus II ?

Today I have observed again a kind of unpredicatable behaviour in quartus II that I had already experienced in another...
16 comments posted 20yrs
posted by oopere
16 comments posted 20yrs posted by oopere

floating point arithemetic on fpga

hi im doing a project to implement single and double precision floating point arithemetic units on Altera FPGA.Can some...
4 comments posted 20yrs
posted by shaz.pecobian
4 comments posted 20yrs posted by shaz.pecobian

Field Programmable Object Array

Hello everyone, is there anyone who knows about the FPOA (Field Programmable Object Array) by Mathstar? Did anyone ever...
2 comments posted 20yrs
posted by tsemertzidis
2 comments posted 20yrs posted by tsemertzidis

Graphics-2-FPGA

Hi, I would like to ask if somebody has come across the same problem: I need to convert a picture (bmp format) to a .he...
5 comments posted 20yrs
posted by mountaineering
5 comments posted 20yrs posted by mountaineering

Platform USB Cable and Windows XP Pro x64

Basically i am looking for a way to get this cable working with the x64 bit version of windows - can somebody help me wi...
2 comments posted 20yrs
posted by
2 comments posted 20yrs posted by

problem in interfacing with SDRAM controller

hi all, I have a core already inside the Spartan 3 FPGA. I m trying to integrate SDRAM Controller with the existing cor...
0 comments posted 20yrs
posted by amirtham
0 comments posted 20yrs posted by amirtham

H for FPGA

% function [h,c_upd]=3DDCD_upd_max(R,N,M,H,Nit,beta,N_upd_max); function [h,M_val,c_it,c_upd]=3DDCD_upd_max(R,N,M,H,Nit...
0 comments posted 20yrs
posted by threeinchnail
0 comments posted 20yrs posted by threeinchnail