H for FPGA

% function [h,c_upd]=3DDCD_upd_max(R,N,M,H,Nit,beta,N_upd_max); function [h,M_val,c_it,c_upd]=3DDCD_upd_max(R,N,M,H,Nit,beta,N_upd_max); % Solving normal equations: R*h=3Dbeta % =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D % R - N x N system matrix (real-valued); % beta - N x 1 right-side vector; % h - N x 1 solution vector; % N - system size; % M - number of bits used for representation of the solution; % Nit - a threshold for number of iterations; % =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D h=3Dzeros(N,1); % solution vector initialisation; delta=3Dzeros(1,2); % plus-minus step-size parameters; c_it=3Dzeros(1,M); % number of iterations (passes) for each bit; c_upd=3Dzeros(1,M); % number of updates for each bit; M_val=3DM; % real number of bits; for m=3D1:M d=3DH*2^(-m); % step-size parameter; delta(1)=3Dd; delta(2)=3D-d; for it=3D1:Nit Flag=3D0; % indicator of successful updates; for p=3D1:N % pass through all elements of h; [val ad]=3Dmin([-beta(p),beta(p),-abs(R(p,p)*d/2)]); if adN_upd_max break; end end if Flag=3D=3D0 c_it(m)=3Dit; break; end if sum(c_upd)>N_upd_max c_it(m)=3Dit; break; end end % it if it=3D=3DNit M_val=3Dm-1; break; end if sum(c_upd)>N_upd_max M_val=3Dm-1; c_it(m)=3Dit; break; end end % m return

I am tried to implement the algorithm above into FPGA. My question is if the H value effects the result in FPGA. Coz I think when the float point changes to fixed-point, the Matrix R and Vector b will change. And I also need change the H. But my tutor said it is for matlab, but for FPGA, the H does not matter to the result. The important parameter is m. Is it true? I don't have much experience on it. Any one can help

me figure it out? Thank you very much.