abel to vhdl converter

I have a JED file for an old PAL device and I have to put this design in a FPGA. Is there a tool that can read the JED file and translate it to any usable language (VHDL prefered)...

Reply to
lingamaneni.naveen
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JED != ABEL. You have only the fusemap!

Yup. It's a sloppy bag of fats and proteins suspended in salty water, and it sits between your ears.

But being just a little more helpful....

It is not too difficult to construct a VHDL *netlist* from a fusemap and a description of the target PAL device, although I'm not aware of any off-the-shelf tools to do it. That could give you a simulation model, but it does NOT give you a behavioural model that would allow you to understand and modify the functionality. With your knowledge of the device's intended functionality and the simulation model, you could write a testbench to exercise it, check out the fine details of its behaviour and use that information to do the reverse engineering.

If the PAL is purely combinatorial (PAL16L8 etc) then you could construct a truth table. If it's a registered device (PAL16R8,

22V10...) then it's a bit harder. In PAL devices register resources were scarce, and designers used all manner of ingerious tricks to cram in the logic; that usually meant obscuring the distinction between control and datapath, so reverse engineering could be fun.
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Reply to
Jonathan Bromley

yea... if you've got the actual abel code, not just the "synthesized" JED file, you're probably better off rewriting the VHDL. I can't imagine that anything that was originally written in ABEL is so complicated that it'd take more than a couple hours to rewrite.... if i'm not mistaken devices were pretty small back when folks where using abel, so it can't feasibly be ALL that much logic to recode.

J>

Reply to
Paul

A long time ago, I found some VHDL models of PALS that used text_io to read the jedec file, and built a constant array that was used to drive a huge generate tree that built up all the and/or gates and flops, etc. The neat thing about it was that the text-io stuff all ran at elaboration time. Too bad synthesis tools cannot make that distinction, and allow text-io for static purposes.

If you find them (it has been a long time since then) you might use them as an guide for converting the fusemap to a vhdl package file (with a perl or c app, etc.) that defines the constant, and then the model could be modified to reference the package constant.

You might even be able to simply edit the jedec file to turn it into a string array constant definition, and then write vhdl that would convert that into the constant format used by the model.

Just an idea...

Andy

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Reply to
Andy

This goes back a long time, but I remember that MachXL software from AMD used to be able to reconstruct source from a .JED file. This required a .JED that contained the symbol table (signal names) to end up with something readable. It unfortunately showed your equations in sum-of-products just the way it went into the PAL, not the pre-compiled source.

If you really have Abel code and not just the JEDEC file, it is my understanding that Xilinx still supports Abel for anything but top level code modules. I still have designs using Abel in lower level modules, but those are supported with the older Foundation 4.1i tools, so I'm not sure you could use them in newer ISE projects.

HTH, Gabor

Reply to
Gabor

Find the utility jed2eqn. Google will turn up some sources. This will give you equations that reasonably easy to modify over to VHDL.

John Adair Enterpo> I have a JED file for an old PAL device and I have to put this design

Reply to
John Adair

Hello Guys, First of all thanks for all of your valuble suggestions.I was able to get the source code (ABEL) for all the PAL's now.Since most of the PAL's were absolute now and for ROHS compliance we are redesigning the board and now we want to replace bulky PAL's around 70 and eight XC3130 series(VHDL) into state of the art FPGA devices.

Coming to my first point

  1. Can i have a VHDL main module and integrate all the individual .ABL files as it is and achieve the same functionality of all the PAL's within FPGA. (With out converting ABEL to VHDL)

  1. Here the board performance (timing of PAL) has to remain the same with high speed FPGA also.Never worked on timing issues till now but heard registering and using flip flop can solve problem any better ideas? (First i am working out on how to get the timing of a PAL from the old board before knowing how to achieve the same timing with in a high speed FPGA )

Sorry for my list of questions and Thanks for being supportive.

Naveen lnaveen snipped-for-privacy@yahoo.com snipped-for-privacy@gmail.com

Gabor wrote:

Reply to
lingamaneni.naveen

Wow, that's some sea-of-pals! What parts are they ?

Does this need to be 'instant-on' ? - or 5V complaint ?

See Gabor's post. This sounds worth trying, perhaps on a couple of Xilinx tool flows (and I think Lattice also have Abel in their flows )

This could be interesting... Trying to actually match timing is not going to be easy. If the PLD code is all Clock-based, then you only need to be 'the same, or faster' on the FPGA.

- but the PLD code may not be quite that clean....

I'd suggest a scan of the Abel sources, and also compile the sources you have (minimal changes, non-merged), to a legal target (XC2C32A?), and read the warnings and fitter report files. The try merge of a couple of sources, into one Abel source file, if you use PIN for the external signals, and nodes for the ones that are only pal-pal, then the tools can optimise if they need to, or use keep if you want to avoid that.

-jg

Reply to
Jim Granville

well there are three different pal's out there. 22v10-15,22v10-10 and

16R8

i d> snipped-for-privacy@gmail.com wrote:

Reply to
lingamaneni.naveen

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