Hi, is there anyone who have a clue on how a synthesizer will do the RTL for bidirectional bus inside your logic? As far as I know high impedence are not synthesizable in the internal logic, only on I/O. Is this correct for all the FPGA? Are there any schematic example on how these bidirectional busses are implemented?
Thanks
Al
The synthesizer infers a tri-buff. Here's a code example:
Sorry, I didn't read the whole question. Synthesis will convert tri-buff inferences to muxes.
-- Mike Treseler
How these muxes look like? Is there any scheme they are arranged? I can imagine it, but I need to understand how many resources that will require. Do you suggest to try to implement it and then look at the rtl view? Can I foresee some structure? Thanks a lot
Al
Sure. Try it and see. It's all LUTs and flops now.
But also look at my netlist .pdfs. You will see lots of muxes, but all of them are inferred from ordinary conditional statements. No Zs required.
-- Mike Treseler
Most synthesis tools, when converting tri-states to muxes assume that the tri-state enables were mutually exclusive (otherwise it would not have worked with tri-states), which allows optimizing the select logic out of the mux, and using simpler and/or trees (implemented with LUTs in an FPGA, of course).
I occasionally use this trick to optimize multiplexor circuits when I know the select lines are mutex, but the synthesis tool does not. I just code it as a 3-state bus, and let it do the conversion.
Andy
Al wrote:
Hi,
your FPGA usually has serveral bus lines. Your synthesis tool will use them.
Bye Helmut
Al wrote:
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