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- stephen.horsford
November 10, 2006, 10:55 am
I am looking for an 8bit * 8 bit pipelined multiplier.
The algorithm I am trying to implement involves:
1 of the 8bits is used as the multiplier and the other, the
multiplicand.
A clock signal is used to activate this process. After the clock cycle:
the first bit of the multiplier is looked at: if it
is a "1", the multiplicand, ie 8 bits are copied into a buffer for
storage, if the first bit is a "0" all zeroes ie. 00000000
are copied into the awaiting buffer.
Secondly, the second bit of the multiplier is looked at, if this is a
"1" the contents of the multiplicand are copied into
the same buffer, but shifted one place to the left. An extra "0" is
thus inserted in the space left after the shift. If the
multiplier bit is a "0", then all zeroes are copied into the same
buffer and shifted one place to the left, with an extra
zero occupying the space left after the shift ie "000000000"
This procedure is continued for all bits of the multiplier, shifting
the product by 3 or 3 or 4 etc. The product results
stored in the same buffer. Therefore this buffer would be kind of
large.
After this "logic coding" exercise we should have 8 products in the
buffer, ie. P0, P1, P2, P3, P4, P5, P6, P7, P8.
As seen above the clock signal is used for synchronization.
After the buffer, other clock signals, attached to the first clock
signal are used to push these products into several
awaiting carry save adders (CSA). These CSA take 3 inputs, one of
course the clock cycle, the others the products P0, P1 etc.
After much research I think this CSA format is in the shape of what is
called a Wallace tree.
After these several summations, two sums are found, these are then
inserted into a CPA, for the final summation. This result
is the product of the 8bit * 8bit pipelined multiplier.
I hope what i've stated above makes sense.
I would really appreciate your assistance as soon as possible, since I
have never used Verilog before.
Any help will be welcomed and appreciated.
Thank You!
Stephen
The algorithm I am trying to implement involves:
1 of the 8bits is used as the multiplier and the other, the
multiplicand.
A clock signal is used to activate this process. After the clock cycle:
the first bit of the multiplier is looked at: if it
is a "1", the multiplicand, ie 8 bits are copied into a buffer for
storage, if the first bit is a "0" all zeroes ie. 00000000
are copied into the awaiting buffer.
Secondly, the second bit of the multiplier is looked at, if this is a
"1" the contents of the multiplicand are copied into
the same buffer, but shifted one place to the left. An extra "0" is
thus inserted in the space left after the shift. If the
multiplier bit is a "0", then all zeroes are copied into the same
buffer and shifted one place to the left, with an extra
zero occupying the space left after the shift ie "000000000"
This procedure is continued for all bits of the multiplier, shifting
the product by 3 or 3 or 4 etc. The product results
stored in the same buffer. Therefore this buffer would be kind of
large.
After this "logic coding" exercise we should have 8 products in the
buffer, ie. P0, P1, P2, P3, P4, P5, P6, P7, P8.
As seen above the clock signal is used for synchronization.
After the buffer, other clock signals, attached to the first clock
signal are used to push these products into several
awaiting carry save adders (CSA). These CSA take 3 inputs, one of
course the clock cycle, the others the products P0, P1 etc.
After much research I think this CSA format is in the shape of what is
called a Wallace tree.
After these several summations, two sums are found, these are then
inserted into a CPA, for the final summation. This result
is the product of the 8bit * 8bit pipelined multiplier.
I hope what i've stated above makes sense.
I would really appreciate your assistance as soon as possible, since I
have never used Verilog before.
Any help will be welcomed and appreciated.
Thank You!
Stephen
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