Hello,
I learned that when a signal is multiplied by an IQ signal, the signal can be down sampled by 2. So assume that I have a signal that samples at 100MS and I multiplied it by an IQ signal. Then I can down sample each I and Q to 50MS. How is it working? Do I need a filter before down sampling? Or can I down sample without any filtering? Any example design that show how I can do this preferably in FPGA?
Best regards