Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15254 Threads Posts
to

How to install xilinx ise8.2 in Madriva linux

Hi guys, I am realy a newbee in the world of linux..Now i want to shift my whole work into linux environment..I install...
1 comments posted 19yrs
posted by subin.82
1 comments posted 19yrs posted by subin.82

Gigabit Ethernet UDP/IP

Hello, for a printing application I would like to receive data from a Unix workstation over Gigabit Ethernet (copper) a...
5 comments posted 19yrs
posted by kfalser
5 comments posted 19yrs posted by kfalser

SDK 8.2 error 127

Does anyone out there use SDK version 8.2? I recently migrated from 8.1 where I never had an issue compiling small piec...
2 comments posted 19yrs
posted by please
2 comments posted 19yrs posted by please

IDELAY and whether pigs can fly...

1) Is the V4 IDELAY resolution 75ps like the switching document says or the 78.125ps mentioned in the forum? 78.125 mak...
4 comments posted 19yrs
posted by mottoblatto
4 comments posted 19yrs posted by mottoblatto

Will FPGAs suit my need?

Hi all, I'm an electronics hobbyist; my projects are generally quite small. They generally consist of me using 7400 chi...
14 comments posted 19yrs
posted by NickHolby
14 comments posted 19yrs posted by NickHolby

XST bug inferring dynamic shift register

Hi, I've got the following Verilog code which selects a variable tap from a delay line: wire [2:0] idly; reg signed [ds...
0 comments posted 19yrs
posted by ebrombaugh.invalid.
0 comments posted 19yrs posted by ebrombaugh.invalid.

FIFO LogiCore with ISE 8.2 ??

Hi all, I've created 2 different FIFO with Xilinx Core Generator. I insert the first one in my design, everything is ok...
0 comments posted 19yrs
posted by matthieu.cattin
0 comments posted 19yrs posted by matthieu.cattin

Stratix RAM limitations

I have a design needing a RAM which Quartus is putting into 2 VERY under-utilized Mega-RAMs instead of the M4Ks I want...
3 comments posted 19yrs
posted by yiannac
3 comments posted 19yrs posted by yiannac

Too many warnings in Modelsim?

Hello, I am developing a solution using Xilinx ISE 8.2 and Modelsim 6.1. When I start the Post Place & Route simulation...
2 comments posted 19yrs
posted by maybetooparanoid
2 comments posted 19yrs posted by maybetooparanoid

xc3sprog

Hi, It's been over two years since I released xc3sprog. Since then Xilinx has released ISEWebPack for GNU/Linux. Many p...
9 comments posted 19yrs
posted by andrew
9 comments posted 19yrs posted by andrew

XMD with Microblaze and EDK 8.2

Hooray! I have finally transfered my projects to ISE/EDK 8.2, with success. *BUT* Everithing works fine, except that I...
0 comments posted 19yrs
posted by me_zara
0 comments posted 19yrs posted by me_zara

16-bit DDR memory controller in EDK

Hi, I need to know is it possible to have a 16-bit PLB DDR memory controller in EDK 8.x for a custom made board. So far...
5 comments posted 19yrs
posted by sheikh.m.farhan
5 comments posted 19yrs posted by sheikh.m.farhan

arbitrator

Hi I need to code an arbitrator for an sdram controller so that two ip block can share access to it. Does anyone know of...
1 comments posted 19yrs
posted by maxascent
1 comments posted 19yrs posted by maxascent