Setup time path on V4 SX w/ IDELAY

I have the following path in an IOTILE:

IBUFDS --> IDELAY (IOBDELAY_TYPE => "FIXED", IOBDELAY_VALUE => 0) -->

FDC

I have a V4 SX55 -11

Here's the output from my map timing:

Slack (setup path): 1.411ns (requirement - (data path - clock path

- clock arrival + uncertainty)) Source: adc1_db_n (PAD) Destination: adc1_iface/id_out_r_11 (FF) Destination Clock: adc_clk rising at 0.000ns Requirement: 8.000ns Data Path Delay: 7.091ns (Levels of Logic = 3) Clock Path Delay: 0.682ns (Levels of Logic = 3) Clock Uncertainty: 0.180ns

Data Path: adc1_db_n to adc1_iface/id_out_r_11 Delay type Delay(ns) Logical Resource(s) ---------------------------- ------------------- Tiopp 1.241 adc1_db_n net (fanout=1) e 0.000 adc1_iface/array_gen[11].diffend_gen.ibufds_inst/SLAVEBUF.DIFFIN Tiodi 0.000 adc1_iface/array_gen[11].diffend_gen.ibufds_inst/IBUFDS net (fanout=1) e 0.274 adc1_iface/ibuf_out Tidockd 5.576 adc1_iface/array_gen[11].idelay_inst adc1_iface/id_out_r_11 ---------------------------- --------------------------- Total 7.091ns (6.817ns logic, 0.274ns route) (96.1% logic, 3.9% route)

I don't understand why the TIDOCKD time is so long. According to the V4 data sheet it should be 0.87ns. While I'm currently meeting timing, I really want this path to be under 3 ns (I had to increase the OFFSET constraint to 8 ns in order to run post-map static timing). At the moment I'm using the IDELAY as a placeholder, but in the future I might want to have a non-zero IOBDELAY_VALUE, so I'd rather keep it.

Any ideas?

Btw, what is the default IOSTANDARD, if not specified in the UCF, for differential and single-ended pins. I thought I remember reading it somewhere, but I can't find that reference anymore.

Thanks,

-Brandon