I'm using Mentor Graphic tools to synthesize my design (Leonardo Spectrum: ASIC and Precision RTL: FPGA).
The problem is I'm not very sure on constraining a multiple clock design using Mentor tools. Someone please share some TCL scripts (LeoSpec & Precision) on constraining multi-clock design. It will be a good reference for me and to other people.
At least, a guideline on this issue. Any suggestions and/or advice are most welcome and highly appreciated.
Thanks in advance,