Constraining Multiple clock design

Hi all,

I'm using Mentor Graphic tools to synthesize my design (Leonardo Spectrum: ASIC and Precision RTL: FPGA).

The problem is I'm not very sure on constraining a multiple clock design using Mentor tools. Someone please share some TCL scripts (LeoSpec & Precision) on constraining multi-clock design. It will be a good reference for me and to other people.

At least, a guideline on this issue. Any suggestions and/or advice are most welcome and highly appreciated.

Thanks in advance,

Reply to
Loading thread data ...

In Precision I would simply use the GUI to constrain the clocks and then cut and paste the resulting SDC constructs from the transcript window into a script. All clock are by default asynchronous but you can put them in the same domain again using the GUI or simply use the -domain argument on create_clock. If you have lots of clocks which are not fixed between runs then look up the get_ports/get_clocks SDC commands in the manual, with this command you can do stuff like:

set clock_list [get_clocks *] or set clock_list {clock1 clock2 clock3}

foreach clk_i $clock_list { create_clock -period .... -name $clock_list ... -domain .... }


formatting link

Reply to

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.