Field-Programmable Gate Arrays

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wintel CPU reads across the PCI Express bus

Hello , Several years ago when I designed my first PCI add -in card for a wintel platform I discovered that back to bac...
2 comments posted 19yrs
posted by pixelsmart
2 comments posted 19yrs posted by pixelsmart

Minimum Speed of DDR / DDR2 SDRAM w/o DLL

I have been unable to find a definitive answer for this in my searches. I would like to operated DDR2 SDRAM below its m...
1 comments posted 19yrs
posted by kevin_neilson
1 comments posted 19yrs posted by kevin_neilson

OPB BRAM not bein detected

I am trying to design a system which has a BLOCK RAM on the OPB Bus , interfaced through a OPB_BRAM_IF_CNTLR. I first a...
0 comments posted 19yrs
posted by get2venu
0 comments posted 19yrs posted by get2venu

picoblaze assembler : kcpsm3.exe and wine/linux

Hi groups, is there something special to get kcpsm3 running on linux/wine ? my wine conf seems ok (FileZila win edition...
4 comments posted 19yrs
posted by rponsard
4 comments posted 19yrs posted by rponsard

CoreABC on M7A3PE600

Hi all, I have a problem with the CoreABC microprocessor from Actel. When I generate this core and program it with samp...
0 comments posted 19yrs
posted by claesvincent
0 comments posted 19yrs posted by claesvincent

MGT RXRECCLK using 3 Global Clocks!

Dear All, I have an ATM/SDH design that uses the Xilinx MGT with 8b/10b disabled and a 10-bit wide interface. I drive t...
0 comments posted 19yrs
posted by simon.stockton
0 comments posted 19yrs posted by simon.stockton

regarding VREF and VCCO and GCLK in virtex 2 pro fpga

hi, i am working on virtex 2 pro fpga i have a basic doubt 1. i am using bank 5 for my input and outputs. i have vref i...
1 comments posted 19yrs
posted by ekavirsrikanth
1 comments posted 19yrs posted by ekavirsrikanth

IP to OPB FIFO

I have an IP core than needs to eventually transfer data such that MicroBlaze (and maybe eventually PowerPC) has access...
3 comments posted 19yrs
posted by mottoblatto
3 comments posted 19yrs posted by mottoblatto

Need FPGA recommendation

I am about to buy the ML403 eval board because I need something to run Linux on, but does anyone know of a similar board...
0 comments posted 19yrs
posted by -
0 comments posted 19yrs posted by -

audio low pass filtering in FPGA

Hello all, I would like to do some simple and dirty DSP to roughly approximate a RC audio filter. I think I can do it s...
6 comments posted 19yrs
posted by mikej
6 comments posted 19yrs posted by mikej

SelectMAP Configuration and Readback

Dear all, I have a requirement to configure one Spartan 3 using another over SelectMAP8. I am struggling to get anythin...
0 comments posted 19yrs
posted by petermendham
0 comments posted 19yrs posted by petermendham

Typical clock frequencies of FPGA designs

Hi, I've been wondering for a while if there is any data about typical clock frequencies of FPGA designs for various FP...
11 comments posted 19yrs
posted by ehliar
11 comments posted 19yrs posted by ehliar

Unable to load FPGA image from the prom

Hello, I am trying to debug a scenario where I am unable to upload the FPGA image from the prom to the FPGA. The image...
1 comments posted 19yrs
posted by kjasapara
1 comments posted 19yrs posted by kjasapara