Latest threads in Field-Programmable Gate Arrays

Need fair opinions on choosing either Altera or Xilinx as main FPGA source

Our design department basically split in the middle with half products were designed with Altera parts and half product...

8 19yrs

jetq5188

8 19yrs jetq5188

wintel CPU reads across the PCI Express bus

Hello , Several years ago when I designed my first PCI add -in card for a wintel platform I discovered that back to bac...

2 19yrs

pixelsmart

2 19yrs pixelsmart

Minimum Speed of DDR / DDR2 SDRAM w/o DLL

I have been unable to find a definitive answer for this in my searches. I would like to operated DDR2 SDRAM below its m...

1 19yrs

kevin_neilson

1 19yrs kevin_neilson

OPB BRAM not bein detected

I am trying to design a system which has a BLOCK RAM on the OPB Bus , interfaced through a OPB_BRAM_IF_CNTLR. I first a...

0 19yrs

get2venu

0 19yrs get2venu

picoblaze assembler : kcpsm3.exe and wine/linux

Hi groups, is there something special to get kcpsm3 running on linux/wine ? my wine conf seems ok (FileZila win edition...

4 19yrs

rponsard

4 19yrs rponsard

CoreABC on M7A3PE600

Hi all, I have a problem with the CoreABC microprocessor from Actel. When I generate this core and program it with samp...

0 19yrs

claesvincent

0 19yrs claesvincent

Athlon X2 or Intel Dual Core for Xilinx ISE tools ?

In this message http://groups.google.it/group/comp.arch.fpga/browse_thread/thread/4b6b9f8a976483ec/8dbea4a95f3e91f7?lnk...

16 19yrs

llandre

16 19yrs llandre

MGT RXRECCLK using 3 Global Clocks!

Dear All, I have an ATM/SDH design that uses the Xilinx MGT with 8b/10b disabled and a 10-bit wide interface. I drive t...

0 19yrs

simon.stockton

0 19yrs simon.stockton

regarding VREF and VCCO and GCLK in virtex 2 pro fpga

hi, i am working on virtex 2 pro fpga i have a basic doubt 1. i am using bank 5 for my input and outputs. i have vref i...

1 19yrs

ekavirsrikanth

1 19yrs ekavirsrikanth

IP to OPB FIFO

I have an IP core than needs to eventually transfer data such that MicroBlaze (and maybe eventually PowerPC) has access...

3 19yrs

mottoblatto

3 19yrs mottoblatto

Is there any version of Aurora protocol which works with LVDS instead of MGTs?

Hi All, I reviewed LocalLink and Aurora protocol and it does not specifically say anything about RocketIO tranceivers....

0 19yrs

shakeri

0 19yrs shakeri

Need FPGA recommendation

I am about to buy the ML403 eval board because I need something to run Linux on, but does anyone know of a similar board...

0 19yrs

-

0 19yrs -

audio low pass filtering in FPGA

Hello all, I would like to do some simple and dirty DSP to roughly approximate a RC audio filter. I think I can do it s...

6 19yrs

mikej

6 19yrs mikej

SelectMAP Configuration and Readback

Dear all, I have a requirement to configure one Spartan 3 using another over SelectMAP8. I am struggling to get anythin...

0 19yrs

petermendham

0 19yrs petermendham

Typical clock frequencies of FPGA designs

Hi, I've been wondering for a while if there is any data about typical clock frequencies of FPGA designs for various FP...

11 19yrs

ehliar

11 19yrs ehliar

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