audio low pass filtering in FPGA

Feb 13, 2007 6 Replies

Hello all,



I would like to do some simple and dirty DSP to roughly approximate a RC audio filter.



I think I can do it something like this (PSEUDO code here, ignoring bit depths and multiplier instantiation issues)



I am aiming for a cut of frequency of ~713 Hz



Audio is an 8 bit unsigned output (from a YM2149 audio chip as it happens) Ena_20K is a single clock enable at my desired sampling frequency (Freq)



wait until rising_edge(clk) if (Ena_20K = '1') then Audio_sampled


There is a motorola booklet describing a stereo graphic equalizer built with a 56001. That would probably have all the logic you would need to do what you want.

If you just want a simple low pass filter, I suppose you don't need that much, but then the 56001 is pretty old by now, so you should be able to do much more.

-- glen

Sounds interesting. I don't suppose you have a link? Google is currently failing me ... Thanks, MikeJ

If you do, every clock,

out = out + (in-out)/k

that approximates a single-pole RC lowpass filter. The divide by K can just be a right-shift by R bits. Ideally you should lose no bits, so if the input is digitized to N bits, do the math to N+R bits width.

(in-out) is of course signed.

If the clock period is T, then for a unit step input, the first output step has amplitude 1/k, so the effective tau is T*k, so the corner frequency is 1/(2*pi*T*K).

I think.

John

Perfect, thanks very much. When I've implemented it will be on the website. Cheers, Mike.

It is older than the web, so it might not be there. (Well, older than when the web started to get popular.)

I might be able to find mine and scan it.

-- glen

Web was developed on a NeXT machine which had DSP56001 in it.

Ancient.....

Just for your information. Cheers!

Satoru

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