I would like to know if you have used the High speed FPGA Tranceivers for source synchronous bus application. In my application, I have 20 bit outgoing and 20 bit incoming bus. Is it possible to do bit to forwarded clock alignement, I was thinking about using precision delay element of 5 ns resolutoin with dynamic range of 3 ns. The data rate I am trying to reach is 6.375 Gbps. Altera Stratix2 GX supports 20 transceivers at 6.375 Gbps.
I would like to get your feedback and share your experience