I would like to know if you have used the High speed FPGA Tranceivers for source synchronous bus application. In my application, I have 20 bit outgoing and 20 bit incoming bus. Is it possible to do bit to forwarded clock alignement, I was thinking about using precision delay element of 5 ns resolutoin with dynamic range of 3 ns. The data rate I am trying to reach is 6.375 Gbps. Altera Stratix2 GX supports 20 transceivers at 6.375 Gbps.
I would like to get your feedback and share your experience
You might check out xilinx app notes xapp265, xapp622 among others.
-Jeff
Thanks for your feedback.
Yes. My data rate requirement is much higher 6.4 Gbps per channel and I have 20 channel that need to run synchronously. The issue with XAPP265 is the it will require a lot of external componets 8:1 serializer and 1:8 deserializer along with 3.2/6.4 GHz clock alignment challenges. But all this is integrated inside the transceivers. This is why I am curious if we can leverage the FPGA transcievers for this application. For data alignment we may be able to use a precise delay element in line with the high speed tranceivers.
What issues do you see in using the Transceivers?
I really appreciate your feedback.
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