Recoding openCV C++ project in pure verilog

I have a 6 month project to work with by hand-recoding openCV C++ project into pure RTL for FPGA usage.
I have a Xilinx Zynq FPGA and I have Vivado.
The code I am using are at
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, and
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Anyone can advise on how to start working on this ? I have been told to scrutinise the code for any maths operations (especially floating) which I am doing now and I need to use the AXI interface and logicore IP for this, right ?
Thanks !
Reply to
Marvin L
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Can you get the algorithm descriptions rather than the C++ code? Optimizing an a implementation of an algorithm for software execution and optimizing it for hardware execution are fairly different beasts.
If you cannot get the algorithm description, your best path will be to create your own from the C++. Things like floating point operations are important, but figuring out how to take advantage of the parallel nature of hardware is crucial.
Good Luck, BobH
Reply to
+1. Sometimes you even want to go as far as rearranging the algorithm to take advantage of the underlying hardware -- processors and FPGA's just do things differently, and that can bubble up pretty far in the design chain.
Tim Wescott 
Control systems, embedded software and circuit design 
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Tim Wescott

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