I've got a project coming up in which one of the things I'm going to need to do is take in the 1 PPS output from a GPS receiver and align it to the 100 MHz frequency reference clock.
The problem here is that the phase relationship is static but undefined. There's plenty of time somewhere to not violate the setup time, but I have to find where it is.
My thought had been to use one of the FPGA PLLs to spin up 8 phases (well, 4 and 4 bar) of the 100 MHz clock and capture the PPS signal on
thermometer code, and figure out what the data phase is. Then I can use the value opposite that and know I've got enough margin to park a semitrailer in.
All well and good, except it dawns on me that I don't know how to convince the tools to make timing for that. Somehow my SDC file has to call for running the input signal from the input pin to 8 flops such that the clock/data skew is less than 1 ns.
Anyone know how I'd do such a thing? Altera seems to support set_max_skew, which might do it if I can disentangle the arcana of the syntax fromBut I'm not necessarily wedded to Altera on this project.