6 years ago
synthesis (Synplify) tools to work with VHDL-2008, but the Lattice tool
itself doesn't seem to understand it. When Diamond analyzes the source
files it complains of syntax errors. The rest of the tool seems to work
just fine and this doesn't stop me from completing the project.
I did an Internet search and found a post at eevblog.com about this from
last year with no response. I put in a ticket to Lattice. I am using a
slightly old version of the tool, 3.3 while the latest is 3.7 I believe.
I hope that's not my problem. lol
-- Rick C