Virtex-4 module based partial reconfiguration problem


I am experimenting on module-based partial reconfiguration for Virtex-4 (LX25-ff668).

Intended functionality is that

After full bitstream download on the board, LED blinks. After partial bitstream download, LED blinks with different frequency.

Intended chip floorplan is that

Left half is is 'reconfigurable' region and right half is 'fixed' region. I intend to generate partial bitstream for the "left half".

I made 1-bit slice-based bus macro for both of Virtex-2 Pro and Virtex-4.

When I tried module-based flow (xapp290) for Virtex-2 Pro on ISE

8.2.03, it works on the board, for both of full bitstream (with size of 1.4MB) and partial bitstream (with size of 50KB).

I tried on Virtex-4 with ISE 8.2.03. Module based tool flow does not create any error. I checked two NCD files for partial / full bitstream on the FPGA editor. Everything seems okay. When I download full bitstream (with size of 955 KB), it works on the board. It means that the bus macro functions correctly as a wire.

Problem is that

-------------------- Partial bitstream size is same as full bitstream size (with 955 KB) Also when I download partial bitstream, it does not work on the board.

It implies that the chip is NOT partitioned as described in UCF file and the generated partial bitstream is not PARTIAL --:


I wonder if we can generate partial bitstream using xapp290 flow for Virtex-4 ? Does anyone have these experiences?

Thank you for any comment.

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Hi Pasacco I was confronted with similar issues while using ISE-6.3 for Virtex-2 Family and the problems persisted for ISE-7.1. Recently I tried with Xiinx early access partial reconfiguration tools; which requires registration to that lounge and things actually worked for me. I suggest you to use early access tools with Xilinx PlanAhead and things would get better.

Hope it works


Pasacco wrote:

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