I am trying to analyze amount of the FPGA (V4) resources used by each of my hierarchical blocks. I am not sure if there is a better way, but I am trying to use the information available in the Floorplanner Design Hierarchy Window. However, I am having difficulty in understanding some of the symbols, which seem to be undocumented, such as MEM16, DPRAM, ISERDES (in this context). I figured that FG probably maps on a LUT, but what about FG5, FG6, etc?...Is there a document available explaining all of these?
Thanks, /Mikhail