Ouputs during startup and Programming

Hi,

I have designed a motor controller with the Virtex 4 FX-12 Mini-Module and I of course would like the PWM output pins to never go high during startup or programming. They do go high during this time like I don't have control over this. Do I need external circuitry to prevent this? I have already fabricated a board and it would be nice if this could be handled without doing something like that. I am using ISE/ EDK 8.2. In my system.ucf file I specify the pins to be outputs. Run away motors are not acceptable at startup or during programming. Thanks for any help.

-Ed

Reply to
Ed
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You should have more thoroughly read the datasheet. Yes, you will need external pull-down resistors. I'm sure the V4 uses a weak-pull up (specified in the datasheet) during this time so you won't need a strong pull-down. I think you'll have to re-work your board.

Reply to
Rob

The cleanest solution is to change the external logic from active High to active Low. Or to insert simple CMOS inverters to achieve the same result. Peter Alfke

Reply to
Peter Alfke

Hello,

One other solution is to use the HSWAP_EN pin of your FPGA...

This pin control the behavior of the user I/O pins (i.e internal pull-ups activated or not) when the FPGA configures itself...

You may apply a high level on the HSWAP pin to disable pull ups, and, on the other hand, connect pull-down resistors on the PWM outputs.

Hope this helps.

With best regards

David Oriot

Peter Alfke wrote:

Reply to
david.oriot

Virtex, Spartan I/O - I/O outputs might transition during configuration

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Within the Answer Record is :

"Xilinx strongly recommends designing systems in such a way that outputs from the device are ignored during configuration."

You might want to read this Answer Record.

Newman

Reply to
Newman

Reply to
Peter Alfke

Ed,

We designed the IO pins so that they are not asserted (i.e. they are kept tristate) while the part is powering ON, and while it is going through its configuration.

Only after "DONE" goes high are the outputs now under the control of the bitstream that the customer has loaded.

For those who want a 'defined' power ON condition, we provide the HSWAPEN pin, so that instead of IO being tristate, we enable the weak pullup for all IOs. Grounding this pin enables the weak pullups on all IO. Tying this pin high disables the weak pullups while configuring.

A 'kludge' (temporary fix) would be to take and add 1K to 10K resistors on the pins that are critical to ground. The IO standard used on these pins would have to be strong enough to drive the resistor loads, and still provide the voltages required. The value of the resistor needs to be determined by the other drive sources at this node (perhaps there is another weak pullup somewhere else?).

Austin

Reply to
Austin Lesea

I think the OP said his board is already designed and thus it might not be a choice to reverse the logic. Also, dead bugging IC's onto a board may be more troublesome than just using pull-downs. CMOS inverters need power and ground, in addition to the signals that you desire to invert, which can make the re-work a bit ugly. I guess it depends on how many signals are affected. If it just a couple then using the resistors is probably the best way to go; but if you're talking about dozens of signals then perhaps octal inverters would be the better choice.

Reply to
Rob

How many PWM pins are involved, and what is their load ?

- some MOSFET drivers have enable pins, and most have internal pulldowns, to give a defined state when the master IC floats. In that case, you would choose the Float-during-config option.

General 'good design' would be to have a separate 'OK to GO" flag, into the driver chips, and that inhibits on many signals, besides FPGA Config Done, you might want to include Low Vcc, wdog, and POST Pass ready signals, before you fire up the 'Big Iron'

-jg

Reply to
Jim Granville

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