Latest threads in Field-Programmable Gate Arrays

Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems

I'm a student in year one, and this is my first, more serious project, so bear with me. I've completed the schematics,...

7 19yrs

tizenharom

7 19yrs tizenharom

My Dear Spartan-3A, Please Please WAKE UP!

After giving up the search for Xilinx supplied MicroBlaze reference designs for Xilinx Spartan-3A kit, I made the refer...

10 19yrs

Antti.Lukats

10 19yrs Antti.Lukats

Xilinx 9.x SW == Total Frustration (so far..)

Its really hard to see how some software manages to get worse and worse every major release! Installed - ISE 9.1+SP3, E...

3 19yrs

Antti.Lukats

3 19yrs Antti.Lukats

Area constraint - trust Low Level Synthesis?

My FPGA is getting a bit crowded. I have a huge distributed FIR in my Spartan3/400. When synthesising the design I get...

1 19yrs

borge.strand

1 19yrs borge.strand

prevent ROM inferration

I have a state machine design with big case statments (VHDL). When I compile with Precision RTL it infers block ROM, wh...

6 19yrs

johannes.hausensteiner

6 19yrs johannes.hausensteiner

Unused Pin setting on per-pin basis

Hi all, I've got a custom FPGA board with a number of peripherals connected to the FPGA. I need to keep the connections...

9 19yrs

ajg112

9 19yrs ajg112

How to Black Box my IP using Quartus II

I want to black-box a sub-module in my design (written in VHDL) that is targeted for a Altera's Cyclone II FPGA. I have...

0 19yrs

futzy.r

0 19yrs futzy.r

DCIRESET in Virtex-4

Hi everybody, My question concerns DCI and temperature. If the temperature of the chip changes considarably between the...

1 19yrs

taileb.mehdi

1 19yrs taileb.mehdi

Xilinx tools concern

Starting a new design using both V2P and V5. I see with concern that the latest Xilinx tools might have issues. We need...

3 19yrs

martin.usenet

3 19yrs martin.usenet

Read 64-bit value over PLB

Hi, My question is straight'n'simple: what's the *most efficient* way of reading a 64-bit value from a slave PLB periph...

3 19yrs

mloulah

3 19yrs mloulah

ISE 8.2 Strange cache problem? Warning...

I am working on a little project using the 8.203i tools. P&R is taking quite a long time now. Was in the middle of a bu...

2 19yrs

lecroy7200

2 19yrs lecroy7200

Where can I find the pass transistor's working curve under 1.2V?

Hi, Please help. Where can I find the pass transistor's working curve under 1.2V that is widely used in IC design prefer...

11 19yrs

wtxwtx

11 19yrs wtxwtx

About ModelSim

Hi, I want to learn using textio. Here I use Read data from scr.txt to IP core RAM and Write them to the text1.txt. I w...

8 19yrs

threeinchnail

8 19yrs threeinchnail

Open source Programmer, Logic Analyzer and In-Circuit Emulator Project

Guys, I saw this on Slashdot and thought of CAF. The PLAICE is an open source hardware and software project developing...

2 19yrs

symon_brewer

2 19yrs symon_brewer

synthesis tools

Hi everybody, I would like to obtain people's opinion on the use of different synthesis tools to target FPGA designs. I...

8 19yrs

axr0284

8 19yrs axr0284

Field-Programmable Gate Arrays

Worth reading in Field-Programmable Gate Arrays