Field-Programmable Gate Arrays

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Xilinx 9.x SW == Total Frustration (so far..)

Its really hard to see how some software manages to get worse and worse every major release! Installed - ISE 9.1+SP3, E...
3 comments posted 19yrs
posted by Antti.Lukats
3 comments posted 19yrs posted by Antti.Lukats

Area constraint - trust Low Level Synthesis?

My FPGA is getting a bit crowded. I have a huge distributed FIR in my Spartan3/400. When synthesising the design I get...
1 comments posted 19yrs
posted by borge.strand
1 comments posted 19yrs posted by borge.strand

prevent ROM inferration

I have a state machine design with big case statments (VHDL). When I compile with Precision RTL it infers block ROM, wh...
6 comments posted 19yrs
posted by johannes.hausensteiner
6 comments posted 19yrs posted by johannes.hausensteiner

Unused Pin setting on per-pin basis

Hi all, I've got a custom FPGA board with a number of peripherals connected to the FPGA. I need to keep the connections...
9 comments posted 19yrs
posted by ajg112
9 comments posted 19yrs posted by ajg112

How to Black Box my IP using Quartus II

I want to black-box a sub-module in my design (written in VHDL) that is targeted for a Altera's Cyclone II FPGA. I have...
0 comments posted 19yrs
posted by futzy.r
0 comments posted 19yrs posted by futzy.r

DCIRESET in Virtex-4

Hi everybody, My question concerns DCI and temperature. If the temperature of the chip changes considarably between the...
1 comments posted 19yrs
posted by taileb.mehdi
1 comments posted 19yrs posted by taileb.mehdi

Xilinx tools concern

Starting a new design using both V2P and V5. I see with concern that the latest Xilinx tools might have issues. We need...
3 comments posted 19yrs
posted by martin.usenet
3 comments posted 19yrs posted by martin.usenet

Read 64-bit value over PLB

Hi, My question is straight'n'simple: what's the *most efficient* way of reading a 64-bit value from a slave PLB periph...
3 comments posted 19yrs
posted by mloulah
3 comments posted 19yrs posted by mloulah

ISE 8.2 Strange cache problem? Warning...

I am working on a little project using the 8.203i tools. P&R is taking quite a long time now. Was in the middle of a bu...
2 comments posted 19yrs
posted by lecroy7200
2 comments posted 19yrs posted by lecroy7200

About ModelSim

Hi, I want to learn using textio. Here I use Read data from scr.txt to IP core RAM and Write them to the text1.txt. I w...
8 comments posted 19yrs
posted by threeinchnail
8 comments posted 19yrs posted by threeinchnail

synthesis tools

Hi everybody, I would like to obtain people's opinion on the use of different synthesis tools to target FPGA designs. I...
8 comments posted 19yrs
posted by axr0284
8 comments posted 19yrs posted by axr0284

Please help me fast !!!!!

I need some vhdl code to configure a xupv2p board and how I'm supose to do the implementation part.
6 comments posted 19yrs
posted by rogodani
6 comments posted 19yrs posted by rogodani

ise9.1i regid not working on x64

..but working fine using 32bit install (bin/nt/setup.exe of the DVD). Anyone have (or have a solution to) this problem?
1 comments posted 19yrs
posted by mleikvol
1 comments posted 19yrs posted by mleikvol