My FPGA is getting a bit crowded. I have a huge distributed FIR in my Spartan3/400. When synthesising the design I get conflicting (?) area constraint messages from Low Level Synthesis and Final Report.
In the first message it looks like my desing doesn't fit, but in the second one it looks OK. Which report should I trust? The part that says I'm using 123% of 3584 slices or the one that says I'm using 3366 of 3584?
The design seems to be working just fine when doing a functional test. But it's a tough job to verify a huge FIR filter and attached dithering.
Thanks for your help interpreting this stuff!
B=F8rge
Low Level Synthesis says:
Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block implementation, actual ratio is 123. Optimizing block to meet ratio 100 (+ 5) of 3584 slices : WARNING:Xst:2254 - Area constraint could not be met for block , final ratio is 123.
But F Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 6,123 out of 7,168 85% Number of 4 input LUTs: 4,939 out of 7,168 68% Logic Distribution: Number of occupied Slices: 3,366 out of
3,584 93% Number of Slices containing only related logic: 3,366 out of
3,366 100% Number of Slices containing unrelated logic: 0 out of
3,366 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 5,793 out of 7,168 80%