Field-Programmable Gate Arrays

DDR2 with Spartan-3A anybody having success??

an unhappy owner of the fresh new Spartan-3A development kit from Xilinx: reason for unhappiness: 1) NO examples how to...

10 comments posted 19yrs

posted by Antti.Lukats

10 comments posted 19yrs posted by Antti.Lukats

weird PACE Error, not one google result

I get the following error in PACE after starting "Assign Package Pins" in ISE 9.1 SP3: ERROR:HDLParsers:3562 - pepExtra...

7 comments posted 19yrs

posted by gyelod

7 comments posted 19yrs posted by gyelod

Xilinx software quality - how low can it go ?!

Hi I really dont understand why Xilinx isnt hiring people who can develop and test software? Is the world-wide shortage...

61 comments posted 19yrs

posted by Antti.Lukats

61 comments posted 19yrs posted by Antti.Lukats

SAE j1850 pwm protocol controller ip core

hi all, can any one send me information about SAE j1850 pwm protocol controller.can i get free verilog or vhdl sources...

0 comments posted 19yrs

posted by ashasravanthi

0 comments posted 19yrs posted by ashasravanthi

Serial FPDP

Hi, Does anyone have details regarding the sFPDP protocol and its implementation? Would be very grateful for any info. I...

0 comments posted 19yrs

posted by eapen.abraham

0 comments posted 19yrs posted by eapen.abraham

DS18B20 connection on FPGA?

Hello all. I'm new to FPGA and I need a little help with connecting Dallas 1-wire temperture DS18B20 sensor. I used tha...

1 comments posted 19yrs

posted by madid87

1 comments posted 19yrs posted by madid87

Macro modified after Map ?

Hi I manually made one MACRO (.nmc file), in V2P30, ISE 8.2.03, for 16-bit AND function using 8 slices. Every LUT was m...

0 comments posted 19yrs

posted by pasacco

0 comments posted 19yrs posted by pasacco

Interconnect architectures : Aurora and SPI-S

I was wondering if anyone had considered the possibility that the new OIF SPI-S using CEI 11G links may be compatible w...

0 comments posted 19yrs

posted by fluxgate

0 comments posted 19yrs posted by fluxgate

CMUcam2 and a XUP-V2Pro

Greetings all, Has anyone connected and used a CMUcam2 to a Digilent XUP-V2Pro FPGA board? If so, how did you do it? Th...

0 comments posted 19yrs

posted by

0 comments posted 19yrs posted by

driving Spartan-3 input from 74LS TTL

I've read answer record 19146 about using a series resistor for 5V tolerance on Spartan 3 inputs. If the signal source...

9 comments posted 19yrs

posted by eric

9 comments posted 19yrs posted by eric

fast arbiters (was Re: How to design an abitration cicuit...)

This is the way I make arbiters: // Concise priority arbiter input [26:0] req; // Bit zero is highest priority wire [26...

5 comments posted 19yrs

posted by jhallen

5 comments posted 19yrs posted by jhallen

How many Xilinx devkits does one need?

Hi I do have have plenty of Xilinx development hardware. I did thinkt hat for sure enough that i can pick up some board...

2 comments posted 19yrs

posted by Antti.Lukats

2 comments posted 19yrs posted by Antti.Lukats

TigerSHARC TS201 to PLX 9656

Hi, Has anyone tried bridging the TS201 TigerSHARC with the PLX 9656 device? I'm trying to implement this in a current...

5 comments posted 19yrs

posted by eapen.abraham

5 comments posted 19yrs posted by eapen.abraham

Is there a reset signal available in verilog in Xilinx FPGAs?

As a sample here is some code. To be clear: I am not looking for alternate ways to code the following always block; I w...

2 comments posted 19yrs

posted by janbeck

2 comments posted 19yrs posted by janbeck

Placement error for adjacent pins

I have two pin one is IN and the other is INOUT and they each one goes to the D input of two FFs clocked by two differe...

4 comments posted 19yrs

posted by mhs000

4 comments posted 19yrs posted by mhs000