Field-Programmable Gate Arrays

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Please help me fast !!!!!

I need some vhdl code to configure a xupv2p board and how I'm supose to do the implementation part.
6 comments posted 19yrs
posted by rogodani
6 comments posted 19yrs posted by rogodani

ise9.1i regid not working on x64

..but working fine using 32bit install (bin/nt/setup.exe of the DVD). Anyone have (or have a solution to) this problem?
1 comments posted 19yrs
posted by mleikvol
1 comments posted 19yrs posted by mleikvol

DDR2 with Spartan-3A anybody having success??

an unhappy owner of the fresh new Spartan-3A development kit from Xilinx: reason for unhappiness: 1) NO examples how to...
10 comments posted 19yrs
posted by Antti.Lukats
10 comments posted 19yrs posted by Antti.Lukats

weird PACE Error, not one google result

I get the following error in PACE after starting "Assign Package Pins" in ISE 9.1 SP3: ERROR:HDLParsers:3562 - pepExtra...
7 comments posted 19yrs
posted by gyelod
7 comments posted 19yrs posted by gyelod

Xilinx software quality - how low can it go ?!

Hi I really dont understand why Xilinx isnt hiring people who can develop and test software? Is the world-wide shortage...
61 comments posted 19yrs
posted by Antti.Lukats
61 comments posted 19yrs posted by Antti.Lukats

SAE j1850 pwm protocol controller ip core

hi all, can any one send me information about SAE j1850 pwm protocol controller.can i get free verilog or vhdl sources...
0 comments posted 19yrs
posted by ashasravanthi
0 comments posted 19yrs posted by ashasravanthi

Serial FPDP

Hi, Does anyone have details regarding the sFPDP protocol and its implementation? Would be very grateful for any info. I...
0 comments posted 19yrs
posted by eapen.abraham
0 comments posted 19yrs posted by eapen.abraham

DS18B20 connection on FPGA?

Hello all. I'm new to FPGA and I need a little help with connecting Dallas 1-wire temperture DS18B20 sensor. I used tha...
1 comments posted 19yrs
posted by madid87
1 comments posted 19yrs posted by madid87

Macro modified after Map ?

Hi I manually made one MACRO (.nmc file), in V2P30, ISE 8.2.03, for 16-bit AND function using 8 slices. Every LUT was m...
0 comments posted 19yrs
posted by pasacco
0 comments posted 19yrs posted by pasacco

Interconnect architectures : Aurora and SPI-S

I was wondering if anyone had considered the possibility that the new OIF SPI-S using CEI 11G links may be compatible w...
0 comments posted 19yrs
posted by fluxgate
0 comments posted 19yrs posted by fluxgate

CMUcam2 and a XUP-V2Pro

Greetings all, Has anyone connected and used a CMUcam2 to a Digilent XUP-V2Pro FPGA board? If so, how did you do it? Th...
0 comments posted 19yrs
posted by
0 comments posted 19yrs posted by

driving Spartan-3 input from 74LS TTL

I've read answer record 19146 about using a series resistor for 5V tolerance on Spartan 3 inputs. If the signal source...
9 comments posted 19yrs
posted by eric
9 comments posted 19yrs posted by eric

How many Xilinx devkits does one need?

Hi I do have have plenty of Xilinx development hardware. I did thinkt hat for sure enough that i can pick up some board...
2 comments posted 19yrs
posted by Antti.Lukats
2 comments posted 19yrs posted by Antti.Lukats

TigerSHARC TS201 to PLX 9656

Hi, Has anyone tried bridging the TS201 TigerSHARC with the PLX 9656 device? I'm trying to implement this in a current...
5 comments posted 19yrs
posted by eapen.abraham
5 comments posted 19yrs posted by eapen.abraham