Help with ATF750CL and WinCUPL

May 07, 2007 2 Replies

I'm trying to code an 'enhanced' binary-to-7segments display decoder with ATF750CL and WinCUPL.



I'm experiencing problems using the truth table CUPL construct , so I wrote these test code lines:



Name ATF750CL; Partno XXXX; Date Apr 2007; Revision 0.0 GEAT Floor Display Decoder; Designer mf; Company c companyname snc, 2007; Assembly Custom; Location Naples; Device v750c;


/* Input pins */ PIN [1..11] = [in1, in2, in3, in4, in5, in6, in7, in8, in9, in10, in11]; PIN 13 = in12;



/* Output pins */ PIN [14..23] = [o1, o2, o3, o4, o5, o6, o7, o8, o9, o10];



FIELD input = [in4, in3, in2, in1] ;



FIELD output = [o7, o8, o9, o10] ; FIELD output2 = [o3, o4, o5, o6] ;



/* Basically the output is a copy of the input */ TABLE input => output { 'b'0000 => 'b'0000; 'b'0001 => 'b'0001; 'b'0010 => 'b'0010; 'b'0011 => 'b'0011; 'b'0100 => 'b'0100; 'b'0101 => 'b'0101; 'b'0110 => 'b'0110; 'b'0111 => 'b'0111; 'b'1000 => 'b'1000; 'b'1001 => 'b'1001; 'b'1010 => 'b'1010; 'b'1011 => 'b'1011; 'b'1100 => 'b'1100; 'b'1101 => 'b'1101; 'b'1110 => 'b'1110; 'b'1111 => 'b'1111; }



/* And this also, but on different output pins */ output2 = input;



Well, 'output2' behaves correctly, while 'output' pins are always at 0 level.



Do you know why?!?!?!?!?!



PLS HELP!!!!



Yes. This is a result of CUPLs internal handling of numeric suffixes. In Cupl IF the VALUE of the suffix is NUMERIC, it matters in TABLE statements. That value is used for the COLUMN alignment ( In most languages, once a variable is named, usage does not care how it is composed. )

So, you have two choices :

Choice A: Remove the trailing numeric, for example, by using an underscore, or a letter. CUPL now uses the Field order, to assign the Table mapping

FIELD input = [in4_..in1_] ; FIELD output = [o10_..o7_] ;

Choice B: Keep the trailing numeric, but align the Table to column match. Note, CUPL starts Table indexes from Zero, and allows X padding, so the column aligned table, for 4..1 and 10..7 suffixes, looks like the one below.

PIN = [in4..in1] ; FIELD input = [in4..in1] ; FIELD output = [o10..o7] ; FIELD output2 = [o6..o3] ;

TABLE input => output { /* 43210 A9876543210 */ 'b'0000x => 'b'0000xxxxxxx; 'b'0001x => 'b'0001xxxxxxx; 'b'0010x => 'b'0010xxxxxxx; 'b'0011x => 'b'0011xxxxxxx; 'b'0100x => 'b'0100xxxxxxx; 'b'0101x => 'b'0101xxxxxxx; 'b'0110x => 'b'0110xxxxxxx; 'b'0111x => 'b'0111xxxxxxx; 'b'1000x => 'b'1000xxxxxxx; 'b'1001x => 'b'1001xxxxxxx; 'b'1010x => 'b'1010xxxxxxx; 'b'1011x => 'b'1011xxxxxxx; 'b'1100x => 'b'1100xxxxxxx; 'b'1101x => 'b'1101xxxxxxx; 'b'1110x => 'b'1110xxxxxxx; 'b'1111x => 'b'1111xxxxxxx; }

Compiles to what you are seeking, o7 =>in1 o8 =>in2 o9 =>in3 o10 =>in4

Wow! I'll try this as soon as possible. The funny thing is I wrote to pldsupport@atmel for help on this and they wrote me a couple emails saying they are still working on the problem... !!! Thankyou by now...

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