Field-Programmable Gate Arrays

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FPGA board for video processing

Hi, I am looking for a new powerful FPGA board for video processing algorithm development. My work will focue on the ar...
4 comments posted 19yrs
posted by hm512
4 comments posted 19yrs posted by hm512

Atom HDL

Hello, Atom is a new high-level hardware description language embedded in the functional language Haskell. Atom compile...
13 comments posted 19yrs
posted by tomahawkins
13 comments posted 19yrs posted by tomahawkins

JTAG Loader tools won't execute

I just wanted to try the JTAG Loader tools provided with PicoBlaze and I cannot run neither hex2svf.exe, nor hex2svfset...
5 comments posted 19yrs
posted by gyelod
5 comments posted 19yrs posted by gyelod

lwIP RAW mode support for V4 temac

Hello, Does anyone know of an example using lwIP in RAW mode with the Virtex-4 temac? From what I understand, the lwIP...
11 comments posted 19yrs
posted by prdubois
11 comments posted 19yrs posted by prdubois

Tcl slash backslash

Hello all, I'm using XP and paths are separated with backslashes. But Tcl uses slashes. How do you handle that, are the...
2 comments posted 19yrs
posted by WeikEngOff
2 comments posted 19yrs posted by WeikEngOff

Prunnning Register missunderstood!!

Hi everybody, After synthesizing my architecture using Synplify pro, i received several same warning like: ... hdl\FSM_...
2 comments posted 19yrs
posted by Amine.Miled
2 comments posted 19yrs posted by Amine.Miled

Select pullup, pulldown or none via embedded S/W

Hi, Within our ASIC library, we have an I/O pad which has input pins allowing us to select whether a pullup, pulldown o...
23 comments posted 19yrs
posted by moogyd
23 comments posted 19yrs posted by moogyd

Use of "blocks" in Quartus design

I'm a fairly experienced user of Quartus but I've never considered using "blocks" in block design files i.e. my design...
4 comments posted 19yrs
posted by David.Wooff
4 comments posted 19yrs posted by David.Wooff

Wait-for / until won't work ? Xilinx Spartan 3

Hello. I'm new to FPGA desing, so could you please help me with this little = problem. To run my sensor I must have som...
25 comments posted 19yrs
posted by madid87-MAKNI-
25 comments posted 19yrs posted by madid87-MAKNI-

PLB master with burst mode

Hi, I build a PLB Master in single byte transfer mode and it works well. Now, I try to use the burst mode and I don't u...
3 comments posted 19yrs
posted by lpaulo07
3 comments posted 19yrs posted by lpaulo07

Video scaler for Spartan 3E?

Hi Just want to do a feasibility study on whether it is possible to design and implement a video scaler on a Spartan 3E...
20 comments posted 19yrs
posted by csoon
20 comments posted 19yrs posted by csoon

Xilinx WebPACK 91i on vmware RHEL4

I am trying to install the Xilinx ISE WebPACK software on a vmware virtual machine running RHEL4-WS. I made the machine...
1 comments posted 19yrs
posted by spamtrap
1 comments posted 19yrs posted by spamtrap

OPB Master Peripheral

Hello all, I am working on a project, in which am trying to make OV7660 camera protoboard to talk to ML300 Xilinx FPGA...
3 comments posted 19yrs
posted by narashimanc
3 comments posted 19yrs posted by narashimanc