Field-Programmable Gate Arrays

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LVDS termination scheme to nonstandard ribbon cable

Hi I am doing a Spartan3 to Spartan 3 interconnect trough a ribbon (flat) cable with a characteristic impedance of 173R...
37 comments posted 19yrs
posted by stefan.elmsted
37 comments posted 19yrs posted by stefan.elmsted

6502 and CPU licences in general

I've found a 6502 core at http://www.sprow.co.uk/fpgas/free6502.htm , which is based on a version from free-ip.com, whi...
16 comments posted 19yrs
posted by fb
16 comments posted 19yrs posted by fb

Error while generating Libraries and BSPs.

Hi, I am at my initial stage of design with a Microblaze which is connected to two peripherals through FSLs. The connec...
0 comments posted 19yrs
posted by shantchandrakar
0 comments posted 19yrs posted by shantchandrakar

SATA OOB detection with Virtex5

Hi to all i would to use SATA OOB detection with Virtex5 GTPs. Iam using the ML505 development board with the two SATA...
2 comments posted 19yrs
posted by al_ko
2 comments posted 19yrs posted by al_ko

fit_timer: trouble connecting interrupt

In my application, I was trying to switch from using an opb_timer to a fit_timer to save on resources, but seem to be h...
1 comments posted 19yrs
posted by cdeleo
1 comments posted 19yrs posted by cdeleo

Custom Memory Initialization

Hi, I need your help for some problem using the Xilinx EDK in simulation and profiling. The system I have designed is c...
0 comments posted 19yrs
posted by giovannibusonera
0 comments posted 19yrs posted by giovannibusonera

Altera Cyclone II - used in 100USD Laptop

http://www.heise.de/mobil/artikel/88916/2 http://www.heise.de/bilder/88916/2/1 pretty interesting - so funny that makes...
3 comments posted 19yrs
posted by Antti.Lukats
3 comments posted 19yrs posted by Antti.Lukats

problem while reading from DDR 2 memory

Hi to all I am currently working on DDR2 controller for Burst Lenth 8. My own code is giving good results when i verifi...
3 comments posted 19yrs
posted by sudhakarmvs
3 comments posted 19yrs posted by sudhakarmvs

clarification: clock doubling in Spartan 3

If we design an S3-based system using an internal clock doubler, the design software wants to know our input frequency....
7 comments posted 19yrs
posted by jjlarkin
7 comments posted 19yrs posted by jjlarkin

Binary to BCD

Hello all. I'm very new to VHDL and stuck with a simple task. This code should convert binary number to BCD number usin...
5 comments posted 19yrs
posted by madid87-MAKNI-
5 comments posted 19yrs posted by madid87-MAKNI-

Project Navigator / Verilog / +define

I'm having a problem with Xilinx Navigator "discovering" a Verilog design hierarchy. I've inherited some IP that requir...
2 comments posted 19yrs
posted by johnp3+nospam
2 comments posted 19yrs posted by johnp3+nospam

Xilinx ML405 / VxWorks 6.3 Bootloader

Hi, Anyone had experience of creating a VxWorks Bootloader that will run on a Xilinx ML40x Evaluation Platform? I have...
0 comments posted 19yrs
posted by rarockley
0 comments posted 19yrs posted by rarockley

DDR SDRAM in custom board

Hi everyone. I have a virtex II pro in a custom board (sundance board) and a Micron MT46V16M16. I use edk to create a d...
0 comments posted 19yrs
posted by pbantunez
0 comments posted 19yrs posted by pbantunez

How the synthesizer acutally works.

Hi guys, To know how the synthesizer behave,i wrote logic to add 4 vectors in three different ways.And i got differnet...
13 comments posted 19yrs
posted by subin.82
13 comments posted 19yrs posted by subin.82

M-RAM allocation in Stratix EPS125B672C6

Hi , I am using Altera Quartus II version 4.0 . The EPS125 device has 138 M4K blocks 224 M512 blocks 2 number of 512K M...
2 comments posted 19yrs
posted by nandits11
2 comments posted 19yrs posted by nandits11