Hello all. I'm very new to VHDL and stuck with a simple task. This code should convert binary number to BCD number using shift and add= 3 =
algoritam
After this code executes I always get "0000" in digit and unit
You don't have to analyze the whole code, just tell me what is generally= =
wrong. Thank you people!
variable temp: bit_vector(7 downto 0) :=3D "00011000"; --24 (10) variable unit: bit_vector(3 downto 0) :=3D "0000"; variable digit: bit_vector(3 downto 0):=3D "0000"; begin for i in 0 to 7 loop digit :=3D digit sll 1; digit(0) :=3D unit(3); unit :=3D unit sll 1; unit(0) :=3D temp(7); temp :=3D temp sll 1; --This is the part where I add 3, is there any other way? It must work= =
on FPGA case digit is when "0101" =3D> digit :=3D "1000"; when "0110" =3D> digit :=3D "1001"; when "0111" =3D> digit :=3D "1010"; when "1000" =3D> digit :=3D "1011"; when "1001" =3D> digit :=3D "1100"; when others =3D> digit :=3D digit; end case; =
case unit is when "0101" =3D> unit :=3D "1000"; when "0110" =3D> unit :=3D "1001"; when "0111" =3D> unit :=3D "1010"; when "1000" =3D> unit :=3D "1011"; when "1001" =3D> unit :=3D "1100"; when others =3D> unit :=3D digit; end case; end loop;