Latest threads in Field-Programmable Gate Arrays

Library unit VPKG is not available in library UNISIM

I am trying to synthesize a code using ISE which contains a component fifo the fifo code is the following -- synopsys t...

1 19yrs

dhruvakshad

1 19yrs dhruvakshad

Using the EDK based video decoder

Hello everybody, I am trying to capture input video data using the Digilent Video Decoder board (VDEC1) connected to th...

0 19yrs

koustav79

0 19yrs koustav79

Interfacing the EDK based video decoder

Hello everybody, I am trying to use the EDK based video decoder design provided by Digilent. But when I am trying to bu...

1 19yrs

koustav79

1 19yrs koustav79

Xilinx XST 9.2i.01 - still incomplete support for always @*

After waiting patiently for Xilinx to support always @* properly, I'm still having problem with this code: localparam i...

3 19yrs

anonymous

3 19yrs anonymous

Enterpoint Web Site

Due to server maintainence our website by our hosting provider and email went down last night. After over-running it's...

0 19yrs

g1

0 19yrs g1

modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"

In modelsim Actel, when I do the post layout simulation, I have a lot of warnings. =BFhow i can take off the vitalglitc...

2 19yrs

dorama2

2 19yrs dorama2

libero.actel

Is possible force the assignation of a number pin (no global pin) to a clock? (=BFcan i do before synthesize?) On synth...

0 19yrs

dorama2

0 19yrs dorama2

regarding specifying clock as internal signal in chipscope

Hi all, i am using chipscope for checking the behavior of the internal signals, i have a problem my differential clock...

2 19yrs

ekavirsrikanth

2 19yrs ekavirsrikanth

JTAG detection

Hello Every1! I am facing one problem and would like to seek help from you people. We have designed one board where "EP...

1 19yrs

suruchi81

1 19yrs suruchi81

Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project

Greetings, all, I have read through many postings about bypass/decoupling capacitors for Xilinx FPGAs at comp.arch.fpga...

14 19yrs

Lue.Her

14 19yrs Lue.Her

Can multiple Ferrite Beads be used to connect ...?

I am designing a board. I splited the ground plane into one analog plan and one digital plane. Can multiple Ferrite Bea...

27 19yrs

dechenxu

27 19yrs dechenxu

BD file generation

HI all, how to generate a buffer descriptor file having filelds: Host address,transfer size,Target address and next poi...

3 19yrs

fazulu.vlsi

3 19yrs fazulu.vlsi

Actel. Libero. Synplify: "unbound component..."

when I synthesize the FPGA (ProASIC PLUS) in Synplify of Libero I have got a lot of warnings: "Unbound component (DFF o...

0 19yrs

dorama2

0 19yrs dorama2

How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?

I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple...

1 19yrs

ssa

1 19yrs ssa

DDR SDRAM in extended military applications

Hi, I am wondering what kind of issues I should look for when designing in DDR SDRAM for extended temperatures. For e.g...

0 19yrs

fpgabuilder-groups

0 19yrs fpgabuilder-groups

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