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How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?

I've figured out how to compile the RTL in Xilinx ISE Webpack9.2i and Altera Quurtus II 7.1. (It just took a few simple RTL-edits.)

But what about the JTAG-debug unit? It seems to use the Lattice's JTAG-block. Can I just replace this with a generic JTAG TAP-controller, and then use a Xilinx-hosted Mico32 with a Lattice download-cable?

Reply to
Ssa
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if you rebuild the lattice jtag-tap then yes. but you have to use fpga regular io pads, not xilinx bscan

antti

Reply to
Antti

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