Is my microblaze cache functioning?

Jul 26, 2007 1 Replies

Hello all,



I am using a Spartan 2E 600-LC development board. When I created the project using the BSB I did not specify the use of caches. I am now trying to enable instruction and data caches. I did not re-open the BSB file as I have added other periperals which I don't want to change.


Can someone confirm the steps needed to enable the cache?



In the MHS file, I have : PARAMETER C_USE_ICACHE = 1 PARAMETER C_CACHE_BYTE_SIZE = 1024 PARAMETER C_USE_DCACHE = 1 PARAMETER C_DCACHE_BYTE_SIZE = 2048 PARAMETER C_ICACHE_BASEADDR = 0x24000000 PARAMETER C_ICACHE_HIGHADDR = 0x25ffffff PARAMETER C_DCACHE_BASEADDR = 0x24000000 PARAMETER C_DCACHE_HIGHADDR = 0x25ffffff



The 32MB of SDRAM starts at 0x2400000, I am using a bootloader.



In the application, I have added:



#include "mb_interface.h" #define ICACHE_SIZE 1024 #define DCACHE_SIZE 2048



main() { microblaze_disable_icache(); microblaze_init_icache_range(0, ICACHE_SIZE); microblaze_enable_icache();



microblaze_disable_dcache(); microblaze_init_dcache_range(0, DCACHE_SIZE); microblaze_enable_dcache();



In the System Assembly > Addresses view, both ICache and DCache boxes are ticked for the SDRAM. Using the debugger I can see that the above disable and enable functions clear and set the ICE and DCE bits in the MSR.


The problem I am having is that the application does not seem to run any faster.



Is there anything else I need to do to enable the cache? What else can I do to verify that the cache is being used?



Is there some sample code which I can run as a benchmark? (something which will show a marked speedup if the cache is functioning?).



Thanks for your help. Mark.



How is your microblaze connected to your external memory? Do you a standard OPB memory controller or do you use one of the multi-channel memory controllers? If you answer the former, what you need is the latter. Then, you interface your microblaze XCL (cachelink) ports directly to the memory controller. The rationale for this strategy is that the microblaze (at least in modern versions) is only designed to cache over XCL.

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