completely open source fpga toolchain

Adam Megacz schrieb:

They used Icarus Verilog for synthesis. Synthesis capability has been removed from icarus Verilog (though the author hopes to reintegrate it one day) since it was very broken and buggy.

Philipp

That's excessively harsh, and equally said of vendors tools with all the bugs they have. There have been enough threads go thru here about those too. So if this is just more open source bashing, please be more specific, and things will get fixed.

Steve (the author of icarus Verilog) does admit that synthesis in the current 0.9 development branch is broken right now, due to some major internal changes in progress, but will be fixed after the 0.9 release is done. During that transition he expects people can continue to use

I'm sure that if you actually report what you think is "very broken and buggy" problems, fixes will appear when he (or others) have time. That that much time between fixes we see for vendors tools which appear at major release cycles.

Steve reports there are others, besides him, working on synthesis backends, and when he gets fixes, he generally applies them to the release tree.

Oh ... two other notes ... at least in progress development trees are visible and available with open source projects, and you can certainly fix problems you find and contribute to the project when you have the skills and time.

Like vendors tools, when releases show up with major bugs, you do the same thing ... keep using the previous release until another major release rolls that you can use (or a patch/update appears).

I remembered snipped-for-privacy@icarus.com, where Steve said:

"CAVEAT: Synthesis in the devel trunk is broken, and has been temporarily abandoned. There was until very recently precious little interest in synthesis, so I didn't let it get in the way of the other tasks I've been working on. Getting synthesis back on line with the devel branch should be a big job.

Therefore, for now I recommend using the 0.8 branch for synthesis work, at least for a proof of concept. If there is interest in putting serious work into it, then getting 0.9 synthesis together can be worked out later."

This is good news, I didn't know that people are working on synthesis backends. Was there a post on geda-user about it?

Philipp

there are or have been sure a while ago I think I got some working AT94K bistream made using the iverilog front

Antti

Just to clear up any confusion here, I am not using the devel trunk.

- a

Just to clear up any confusion here, I am not using the devel trunk.

- a

I just found out about your work by your post on geda-user and am interested to know what the "current projects" are you mentioned in the FCCM paper. Are there any slipway parts left? If not I'll be making two, (or more) for geda-user folk, done with gEDA tools and put up on one of my sites and/or yours.

WIX looks good too!

John Griessen Ecosensory

Dunno ... don't watch that email. Just relayed a comment from private email from Steve.

I responded because of your unkind, broad, unqualified, slamming assessment of Steve's work:

Development branches are expected to be sometimes broken and buggy, but you unjustifiably slammed Steve's work without that qualification. I, and others, have used Steve's synthesis in past stable releases without problems .... as well as Steve, for paying work. The issues I've had with it have all been relatively minor ... and not unlike similar problems with vendors tool chains.

Not knowing where people are using it and NOT having problems, does give most open source developers a vacumn for judging both what is being used, and how much.